SLASEW8A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

all minimum and maximum specifications at –40°C ≤ TA ≤ +125°C; typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53701-Q1 10 Bits
DAC43701-Q1 8
INL Relative accuracy(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error Code 0d into DAC, external reference, VDD = 5.5 V 6 12 mV
Code 0d into DAC, internal reference, gain = 4 ×, VDD = 5.5 V 6 15
Zero-code-error temperature coefficient ±10 µV/°C
Offset error(2) –0.6 0.25 0.6 %FSR
Offset-error temperature coefficient(2) ±0.0003 %FSR/°C
Gain error(2) –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(2) ±0.0008 %FSR/°C
Full-scale error 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom –1 0.5 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom –0.5 0.25 0.5
Full-scale-error temperature coefficient ±0.0008 %FSR/°C
OUTPUT CHARACTERISTICS
Output voltage Reference tied to VDD 0 5.5 V
CL Capacitive load(3) RL = Infinite, phase margin = 30° 1 nF
RL = 5 kΩ, phase margin = 30° 2
Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA,
VDD = 5.5 V		 0.4 mV/mA
Short circuit current VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 10 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 25
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50
Output voltage headroom(1) To VDD, DAC output unloaded, internal reference = 1.21 V, VDD ≥ 1.21 × gain + 0.2 V 0.2 V
To VDD, DAC output unloaded, reference tied to VDD 0.8 %FSR
To VDD, ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V, DAC code = full scale 10
VOUT dc output impedance DAC output enabled and DAC code = midscale 0.25 Ω
DAC output enabled and DAC code = 8d for 10-bit resolution and code = 2d for 8-bit resolution 0.25
DAC output enabled and DAC code = 1016d for 10-bit resolution and code = 254d for 8-bit resolution 0.26
ZO VFB dc output impedance(4) DAC output enabled, DAC reference tied to VDD (gain = 1 ×) or internal reference (gain = 1.5 × or 2 ×) 160 200 240 kΩ
DAC output enabled, internal VREF, gain = 3 × or 4 × 192 240 288
VOUT + VFB dc output leakage(3) At start up, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V 7 nA
Power supply rejection ratio (dc) Internal VREF, gain = 2 ×, DAC at midscale;
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 8 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 12
Slew rate VDD = 5.5 V 1 V/µs
Power-on glitch magnitude At start-up, DAC output disabled, RL = 5 kΩ,
CL = 200 pF		 75 mV
At start-up, DAC output disabled, RL = 100 kΩ 200
Output enable glitch magnitude DAC output disabled to enabled, DAC registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 34 µVPP
Internal VREF, gain = 4 ×, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 70
Output noise density Measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√Hz
Internal VREF, gain = 4 ×, measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.7
Power supply rejection ratio (ac)(4) Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB
Code change glitch impulse ±1-LSB change around midcode (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1-LSB change around midcode (including feedthrough) 15 mV
Function generator TIME-STEP accuracy ±6.25 %
VOLTAGE REFERENCE
Initial accuracy 1.212 V
Reference output temperature coefficient(3) 65 ppm/°C 
EEPROM
Endurance(3) –40°C ≤ TA ≤ +85°C  20000 Cycles
TA > 85°C  1000
Data retention(3) 50 Years
TA = 125°C  20
EEPROM programming write cycle time(3) 10 20 ms
DIGITAL INPUTS
Digital feedthrough DAC output static at midscale, fast-mode plus, SCL toggling 20 nV-s
Pin capacitance Per pin 10 pF
POWER
Load capacitor - CAP pin(3) 0.5 15 µF
IDD Current flowing into VDD Normal mode, DACs at full scale, digital pins static 0.225 0.55 mA
DAC power down, internal reference power down 80 µA
(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. For internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution.
(2) Measured with DAC output unloaded. For 10-bit resolution, between end-point codes: 8d to 1016d and for 8-bit resolution, between end-point codes: 2d to 254d.
(3) Specified by design and characterization, not production tested.
(4) Specified with 200-mV headroom with respect to reference value when internal reference is used.