SLAS536D September 2007 – November 2021 DAC5662A
PRODUCTION DATA
The data input ports of the DAC5662A accept a standard positive coding with data bit D11 being the most significant bit (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance will typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified limits.
All digital inputs of the DAC5662A are CMOS compatible. Figure 7-1 and Figure 7-2 show schematics of the equivalent CMOS digital inputs of the DAC5662A. The pullup and pulldown circuitry is approximately equivalent to 100kΩ. The 12-bit digital data input follows the offset positive binary coding scheme. The DAC5662A is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.