SGLS386F January   2009  – October 2014 DAC5670-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Digital Electrical Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 DLL Usage
      3. 8.3.3 Clock Input
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
      7. 8.3.7 Sleep Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Format
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Definitions of Specifications and Terminology
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • GEM|192
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Ball Grid Array
192 Pins
po_BGA_gls386.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
DACCLK_P K14 I External clock, sample clock for the DAC
DACCLK_N L14 I Complementary external clock, sample clock for the DAC
DLYCLK_P A7 O DDR-type data clock to data source
DLYCLK_N A6 O DDR-type data clock to data source complementary signal
DTCLK_P A9 I Input data toggling reference bit
DTCLK_N A8 I Input data toggling reference bit, complementary signal
DA_P[13] J13 I Port A data bit 13 (MSB)
DA_N[13] K13 I Port A data bit 13 complement (MSB)
DA_P[12] J14 I Port A data bit 12
DA_N[12] H14 I Port A data bit 12 complement
DA_P[11] H13 I Port A data bit 11
DA_N[11] G13 I Port A data bit 11 complement
DA_P[10] G14 I Port A data bit 10
DA_N[10] F14 I Port A data bit 10 complement
DA_P[9] F13 I Port A data bit 9
DA_N[9] E13 I Port A data bit 9 complement
DA_P[8] E14 I Port A data bit 8
DA_N[8] D14 I Port A data bit 8 complement
DA_P[7] C12 I Port A data bit 7
DA_N[7] C11 I Port A data bit 7 complement
DA_P[6] D12 I Port A data bit 6
DA_N[6] D11 I Port A data bit 6 complement
DA_P[5] C13 I Port A data bit 5
DA_N[5] D13 I Port A data bit 5 complement
DA_P[4] B14 I Port A data bit 4
DA_N[4] C14 I Port A data bit 4 complement
DA_P[3] A13 I Port A data bit 3
DA_N[3] A12 I Port A data bit 3 complement
DA_P[2] A11 I Port A data bit 2
DA_N[2] A10 I Port A data bit 2 complement
DA_P[1] B10 I Port A data bit 1
DA_N[1] B11 I Port A data bit 1 complement
DA_P[0] B8 I Port A data bit 0 (LSB)
DA_N[0] B9 I Port A data bit 0 complement (LSB)
DB_P[13] B7 Port B data bit 13 (MSB)
DB_N[13] B6 I Port B data bit 13 complement (MSB)
DB_P[12] A4 I Port B data bit 12
DB_N[12] A5 I Port B data bit 12 complement
DB_P[11] B4 I Port B data bit 11
DB_N[11] B5 I Port B data bit 11 complement
DB_P[10] A3 I Port B data bit 10
DB_N[10] A2 I Port B data bit 10 complement
DB_P[9] B1 I Port B data bit 9
DB_N[9] C1 I Port B data bit 9 complement
DB_P[8] C2 I Port B data bit 8
DB_N[8] D2 I Port B data bit 8 complement
DB_P[7] E1 I Port B data bit 7
DB_N[7] D1 I Port B data bit 7 complement
DB_P[6] D3 I Port B data bit 6
DB_N[6] D4 I Port B data bit 6 complement
DB_P[5] F2 I Port B data bit 5
DB_N[5] E2 I Port B data bit 5 complement
DB_P[4] J1 I Port B data bit 4
DB_N[4] H1 I Port B data bit 4 complement
DB_P[3] G1 I Port B data bit 3
DB_N[3] F1 I Port B data bit 3 complement
DB_P[2] J2 I Port B data bit 2
DB_N[2] K2 I Port B data bit 2 complement
DB_P[1] K1 I Port B data bit 1
DB_N[1] L1 I Port B data bit 1 complement
DB_P[0] M1 I Port B data bit 0 (LSB)
DB_N[0] N1 I Port B data bit 0 complement (LSB)
IOUT_P M7 O DAC current output. Full scale when all input bits are set 1.
IOUT_N M6 O DAC complementary current output. Full scale when all input bits are 0.
RBIASOUT P5 O Rbias resistor current output
RBIASIN P4 I Rbias resistor sense input
CSCAP P3 O Current source bias voltage
CSCAP_IN P2 I Current source bias voltage sense input
REFIO L3 O Bandgap reference output
REFIO_IN L4 I Bandgap reference sense input
RESTART M12 I Resets DLL when high. Low for DLL operation. High for using external setup/hold timing.
LVDS_HTB P9 I DLYCLK_P/N control, LVDS mode when high, ht mode when low
INV_CLK L12 I Inverts the DLL target clocking relationship when high. Low for normal DLL operation. See DLL Usage.
SLEEP P11 I Active-high sleep
NORMAL P13 I High for {a0,b0,a1,b1,a2,b2, …} normal mode
A_ONLY N10 I High for {a0,a0,a1,a1,a2,a2, …} A_only mode
A_ONLY_INV P12 I High for {a0,-a0, a1,-a1,a2,-a2, ...} A_only_inv mode
A_ONLY_ZS N13 I High for {a0,0,a1,0,a2,0, …} A_only_zs mode

Pin Assignments (Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14
A DB10_N DB10_P DB12_P DB12_N DLYCLK _N DLYCLK _P DTCLK_N DTCLK_P DA2_N DA2_P DA3_N DA3_P
B DB9_P GND GND DB11_P DB11_N DB13_N DB13_P DA0_P DA0_N DA1_P DA1_N GND GND DA4_P
C DB9_N DB8_P AVDD AVDD AVDD GND GND GND GND AVDD DA7_N DA7_P DA5_P DA4_N
D DB7_N DB8_N DB6_P DB6_N AVDD AVDD AVDD AVDD AVDD AVDD DA6_N DA6_P DA5_N DA8_N
E DB7_P DB5_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD DA9_N DA8_P
F DB3_N DB5_P GND AVDD GND GND GND GND GND GND AVDD GND DA9_P DA10_N
G DB3_P AVDD GND AVDD GND GND AVDD AVDD GND GND AVDD GND DA11_N DA10_P
H DB4_N AVDD GND AVDD GND GND AVDD AVDD GND GND AVDD GND DA11_P DA12_N
J DB4_P DB2_P GND AVDD GND GND GND GND GND GND AVDD GND DA13_P DA12_P
K DB1_P DB2_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD DA13_N Dacclk_P
L DB1_N AVDD REFIO REFIO _IN AVDD AVDD AVDD AVDD AVDD AVDD GND Inv_clk AVDD Dacclk_N
M DB0_P GND AVDD AVDD AVDD IOUT_N IOUT_P GND GND AVDD GND Restart GND
N DB0_N GND GND AVDD GND GND GND GND GND A_only A_only_z GND
P CSCap _IN CSCap RBIAS_IN RBIAS _OUT GND GND LVDS _htb AVDD Sleep A_only _inv M _Normal

Pin Assignments (Bottom View)

A B C D E F G H J K L M N P
1 DB9_P DB9_N DB7_N DB7_P DB3_N DB3_P DB4_N DB4_P DB1_P DB1_N DB0_P DB0_N
2 DB10_N GND DB8_P DB8_N DB5_N DB5_P AVDD AVDD DB2_P DB2_N AVDD GND GND CSCap _IN
3 DB10_P GND AVDD DB6_P AVDD GND GND GND GND AVDD REFIO AVDD GND CSCap
4 DB12_P DB11_P AVDD DB6_N AVDD AVDD AVDD AVDD AVDD AVDD REFIO _IN AVDD AVDD RBIAS_IN
5 DB12_N DB11_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD GND RBIAS _OUT
6 DLYCLK _N DB13_N GND AVDD GND GND GND GND GND GND AVDD IOUT_N GND
7 DLYCLK _P DB13_P GND AVDD GND GND AVDD AVDD GND GND AVDD IOUT_P GND GND
8 DTCLK_N DA0_P GND AVDD GND GND AVDD AVDD GND GND AVDD GND GND GND
9 DTCLK_P DA0_N GND AVDD GND GND GND GND GND GND AVDD GND GND LVDS_htb
10 DA2_N DA1_P AVDD AVDD GND GND GND GND GND GND AVDD AVDD A_only AVDD
11 DA2_P DA1_N DA7_N DA6_N AVDD AVDD AVDD AVDD AVDD AVDD GND GND Sleep
12 DA3_N GND DA7_P DA6_P AVDD GND GND GND GND AVDD Inv_clk Restart A_only _inv
13 DA3_P GND DA5_P DA5_N DA9_N DA9_P DA11_N DA11_P DA13_P DA13_N AVDD GND A_only_z M _Normal
14 DA4_P DA4_N DA8_N DA8_P DA10_N DA10_P DA12_N DA12_P Dacclk_P Dacclk_N GND