SLLS853F August   2007  – January 2015 DAC5682Z

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics — DC Specification
    6. 7.6 Electrical Characteristics — AC Specification
    7. 7.7 Electrical Characteristics (Digital Specifications)
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FIR Filters
      2. 8.3.2  Coarse Mixers: CMIX0 and CMIX1
      3. 8.3.3  Clock Inputs
      4. 8.3.4  LVDS Data Interfacing
      5. 8.3.5  LVDS Inputs
      6. 8.3.6  LVDS SYNCP/N Operation
      7. 8.3.7  DLL Operation
      8. 8.3.8  CMOS Digital Inputs
      9. 8.3.9  Reference Operation
      10. 8.3.10 DAC Transfer Function
      11. 8.3.11 DAC Output SINC Response
      12. 8.3.12 Analog Current Outputs
      13. 8.3.13 Designing the PLL Loop Filter
      14. 8.3.14 Test Methodology
    4. 8.4 Device Functional Modes
      1. 8.4.1 Dual-Channel Real Upconversion
      2. 8.4.2 Clock and Data Modes
      3. 8.4.3 PLL Clock Mode
      4. 8.4.4 Recommended Multi-DAC Synchronization Procedure Multi-DAC Synchronization Procedure
      5. 8.4.5 Digital Self Test Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Register Name: STATUS0 - Address: 0x00, Default = 0x03
      2. 8.6.2  Register Name: CONFIG1 - Address: 0x01, Default = 0x10
      3. 8.6.3  Register Name: CONFIG2 - Address: 0x02, Default = 0xC0
      4. 8.6.4  Register Name: CONFIG3 - Address: 0x03, Default = 0x70
      5. 8.6.5  Register Name: STATUS4 - Address: 0x04, Default = 0x00
      6. 8.6.6  Register Name: CONFIG5 - Address: 0x05, Default = 0x00
      7. 8.6.7  Register Name: CONFIG6 - Address: 0x06, Default = 0x0C
      8. 8.6.8  Register Name: CONFIG7 - Address: 0x07, Default = 0xFF
      9. 8.6.9  Register Name: CONFIG8 - Address: 0x08, Default = 0x00
      10. 8.6.10 Register Name: CONFIG9 - Address: 0x09, Default = 0x00
      11. 8.6.11 Register Name: CONFIG10 - Address: 0x0A, Default = 0x00
      12. 8.6.12 Register Name: CONFIG11 - Address: 0x0B, Default = 0x00
      13. 8.6.13 Register Name: CONFIG12 - Address: 0x0C, Default = 0x00
      14. 8.6.14 Register Name: CONFIG13 - Address: 0x0D, Default = 0x00
      15. 8.6.15 Register Name: CONFIG14 - Address: 0x0E, Default = 0x00
      16. 8.6.16 Register Name: CONFIG15 - Address: 0x0F, Default = 0x00
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Digital Interface and Clocking Considerations for Application Examples
      2. 9.3.2 Single Complex Input, Real IF Output Radio
      3. 9.3.3 Dual Channel Real IF Output Radio
      4. 9.3.4 Direct Conversion Radio
      5. 9.3.5 CMTS/VOD Transmitter
      6. 9.3.6 High-Speed Arbitrary Waveform Generator
    4. 9.4 Initialization Set Up
      1. 9.4.1 Recommended Start-up Sequence
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. An external RF quadrature modulator then performs the final single sideband up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency plan flexibility while enabling higher output DAC rates to simplify image rejection filtering.

The DAC5682Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family include the interpolating DAC5681Z and the noninterpolating DAC5681.