The DAC80004/70004/60004 (DACx0004) are highly accurate, low-power, voltage-output, quad-channel, 16-, 14-, 12-bit digital-to-analog converters (DACs) respectively. The DACx0004 devices are ensured monotonic by design and offer excellent linearity of less than 1 LSB (Max). The reference input of the DAC is buffered internally using a dedicated reference buffer.
The DACx0004 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale or mid scale depending on status of the POR pin and remains in this state until a valid code is written to the device. These devices consume very low current of 1 mA/channel making them ideal for portable, battery-operated equipment. These devices also contain a power-down feature that reduces current consumption to typically 3 µA at 5 V.
The DACx0004 devices use a versatile 4- or 3-wire serial interface that operates at clock rates up to 50 MHz. The DACx0004 devices also include a SDO pin to daisy chain multiple devices. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACx0004 devices are offered in easy-to-assemble 14-pin TSSOP packages or an ultra small 14-pin VSON package and are fully specified over the extended industrial temperature range of –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DACx0004 | VSON (14) | 3.00 mm x 4.00 mm |
DACx0004 | TSSOP (14) | 5.00 mm x 4.40 mm |
Changes from C Revision (August 2016) to D Revision
Changes from B Revision (June 2016) to C Revision
Changes from A Revision (June 2016) to B Revision
Changes from * Revision (April 2016) to A Revision
DEVICE | RESOLUTION |
---|---|
DAC80004 | 16 |
DAC70004 | 14 |
DAC60004 | 12 |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NUMBER | |||
CLR | 9 | Digital Input | Clear DAC pin, falling edge sensitive | |
GND | 12 | Power | Ground | |
LDAC | 1 | Digital Input | Load DAC pin, active low | |
POR | 6 | Digital Input | Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale. | |
REFIN | 7 | Analog Input | Voltage reference input for all channels | |
SCLK | 14 | Digital Input | Serial interface shift clock | |
SDIN | 13 | Digital Input | Serial interface digital input | |
SDO | 8 | Digital Output | Serial interface digital output for readback and daisy chaining | |
SYNC | 2 | Digital Input | Serial interface synchronization, active low | |
VDD | 3 | Power | Positive power supply (2.7 V to 5.5 V) | |
VOUTA | 4 | Analog Output | DAC A output | |
VOUTB | 11 | Analog Output | DAC B output | |
VOUTC | 5 | Analog Output | DAC C output | |
VOUTD | 10 | Analog Output | DAC D output |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage, VDD to GND | –0.3 | 7 | V | |
Voltage, digital input or output to GND | –0.3 | VDD + 0.3 | V | |
Voltage, analog input (REFIN) or output (VOUTx) to GND | –0.3 | VDD + 0.3 | V | |
Input current to any pin except supply pins | –10 | 10 | mA | |
Maximum junction temperature | 150 | °C | ||
Storage temperature range, Tstg | -60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Voltage, VDD to GND | 2.7 | 5.5 | V | ||
Voltage, analog input (REFIN) or output (VOUTx) to GND | 2.7 V ≤ VDD ≤ 4.5 V | 2.2 | VDD – 0.2 | V | |
4.5 V ≤ VDD ≤ 5.5 V | 2.2 | VDD | V | ||
Ambient Operating Temperature, TA | -40 | 125 | °C |
THERMAL METRIC(1) | DACx0004 | UNIT | ||
---|---|---|---|---|
DMD (VSON) | PW (TSSOP) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 39.6 | 99.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 27.3 | 23.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.0 | 42.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 8.9 | 42.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.5 | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE(2) | ||||||
Resolution | DAC80004 | 16 | Bits | |||
DAC70004 | 14 | |||||
DAC60004 | 12 | |||||
INL | Relative accuracy(1) | ±1 | LSB | |||
DNL | Differential nonlinearity(1) | Ensured monotonic | ±1 | LSB | ||
TUE | Total unadjusted error(1) | TA = +20°C to +40°C | 1.5 | mV | ||
TA = –40°C to +125°C | 2 | |||||
ZCE | Zero code error | TA = –40°C to +125°C, Code 0d into DAC | ±0.2 | ±2 | mV | |
TA = +25°C, Code 0d into DAC | ±0.1 | |||||
ZCE-TC | Zero code error TC | TA = –40°C to +125°C | ±5 | µV/°C | ||
OE | Offset error(1) | TA = +20°C to +40°C | ±1.2 | mV | ||
TA = –40°C to +125°C | ±0.2 | ±1.8 | ||||
TA = +25°C | ±0.2 | |||||
OE-TC | Offset error drift | TA = –40°C to +125°C | ±4 | µV/°C | ||
FSE | Full-scale error(5) | TA = +20°C to +40°C, Code 65535d into DAC | ±0.05 | %FSR | ||
TA = –40°C to +125°C, Code 65535d into DAC | ±0.01 | ±0.07 | %FSR | |||
TA = +25°C | ±0.01 | |||||
FSE-TC | Full-scale error drift(5) | TA = –40°C to +125°C | ±2 | ppm FSR/°C | ||
GE | Gain error(1) | TA = –40°C to +125°C | ±0.005 | ±0.05 | %FSR | |
TA = +25°C | ±0.005 | |||||
GE-TC | Gain drift | TA = –40°C to +125°C | ±2 | ppm FSR/°C | ||
Output voltage drift vs.Time | TA = +25°C, Vout = ¾ of full scale, 1900 hr | 20 | ppm FSR | |||
Load Regulation | TA = +25°C, Vout =Mid Scale | 0.003% | ||||
PSRR | DC Power supply rejection ratio(5) | TA = +25°C, Vout = full scale | –92 | dB | ||
DYNAMIC PERFORMANCE | ||||||
Output voltage settling time | ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, Cload = 200 pF to GND | 5.8 | 8 | µs | ||
Slew rate | 1.5 | V/µs | ||||
Power-up time(3) | 100 | µs | ||||
Power-on glitch energy | Supply slew rate <5 V/msec | 8 | mV | |||
Power-off glitch energy | DAC in power down mode (1 kΩ-GND), Supply slew rate <5 V/msec | 7 | mV | |||
Output noise | 0.1 Hz to 10 Hz | 5 | µVpp | |||
100 kHz BW | 100 | µVRMS | ||||
Output noise density | Measured at 1 kHz | 60 | nV/√Hz | |||
Measured at 10 kHz | 55 | |||||
THD | Total harmonic distortion | REFIN = 3 V ± 0.2 Vpp, Frequency = 10 kHz, DAC at mid scale, specified by design | –80 | dB | ||
PSRR | AC power supply rejection ratio | 200 mV 50 Hz and 60 Hz sine wave superimposed on power supply voltage (AC analysis) | -90 | dB | ||
Code change glitch impulse | 1 LSB change around major carry, Software LDAC mode | 1 | nV-s | |||
Channel-to-channel AC (analog) crosstalk | Full-scale swing on adjacent channel, Hardware LDAC mode | 1 | nV-s | |||
Channel-to-channel DC crosstalk | Full-scale swing on adjacent channels, Measured channel at zero scale | 1 | LSB | |||
Full-scale swing on all channel, Measured channel at zero scale | 1 | |||||
Digital crosstalk | DAC code mid scale, Adjacent input buffer change from 0000h to FFFFh or vice versa | 0.2 | nV-S | |||
Reference feedthrough | REFIN = 3 V ± 0.86 Vpp, Frequency = 100 Hz to 100 kHz, DAC at zero scale | –85 | dB | |||
Digital feedthrough | At SCLK = 1 MHz, DAC output static at mid scale | 0.2 | nV-s | |||
OUTPUT CHARACTERISTICS | ||||||
Voltage range | 0 | VDD | V | |||
Headroom | Output loaded 5 kΩ, DAC code FFFFh | 0.1 | V | |||
Output loaded 0.5 kΩ, DAC code FFFFh | 10 | %FSR | ||||
RL | Resistive load | 0.5 | kΩ | |||
CL | Capacitive load | RL = ∞ | 1 | nF | ||
RL = 5 kΩ | 2 | |||||
RO | DC output impedance | Normal mode | 0.5 | Ω | ||
Power down with 100 kΩ network | 100 | kΩ | ||||
Power down with 1 kΩ network | 1 | kΩ | ||||
Short circuit current | 36 | mA | ||||
VOLTAGE REFERENCE INPUT | ||||||
Reference input range | 2.7 V ≤ VDD ≤ 4.5 V | 2.2 | VDD – 0.2 | V | ||
4.5 V ≤ VDD ≤ 5.5 V | 2.2 | VDD | ||||
Reference input current | 450 | µA | ||||
Reference input impedance | 15 | kΩ | ||||
Reference input capacitance | 10 | pF | ||||
MBW | Multiplying bandwidth | 340 | kHz | |||
DIGITAL INPUTS | ||||||
VIH | High-level input voltage | 2.3 | V | |||
VIL | Low-level input voltage | 0.7 | V | |||
Input leakage | 0 < VDIGITAL INPUT < VDD | ±1 | µA | |||
Pin capacitance | 4 | pF | ||||
DIGITAL OUTPUTS | ||||||
VOH | High-level output voltage | IOH = 2 mA | VDD – 1 | V | ||
VOL | Low-level output voltage | IOL = 2 mA | 0.7 | V | ||
Pin capacitance | 7 | pF | ||||
POWER SUPPLY REQUIREMENTS | ||||||
VDD | Supply voltage | 2.7 | 5.5 | V | ||
IVDD | Supply current | TA = –40°C to +125°C, Normal mode | 4 | 5.5 | mA | |
TA = –40°C to +125°C, Power-down mode | 3 | 7 | µA | |||
Power dissipation | TA = –40°C to +125°C, Normal mode | 20 | mW | |||
TEMPERATURE RANGE | ||||||
TA | Specified performance | –40 | 125 | °C |
4.5 V ≤ VDD ≤ 5.5 V | 2.7 V ≤ VDD ≤ 4.5 V | UNIT | ||||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
SERIAL WRITE and READ | ||||||||
tc | SCLK cycle time | 20 | 40 | ns | ||||
tw1 | SCLK high pulse duration | 10 | 20 | ns | ||||
tw2 | SCLK low pulse duration | 10 | 20 | ns | ||||
tsu | SYNC to SCLK falling edge setup time | 15 | 30 | ns | ||||
tsu1 | Data setup time | 5 | 10 | ns | ||||
th1 | Data hold time | 5 | 10 | ns | ||||
td1 | SCLK falling edge to SYNC rising edge delay time | 5 | 10 | ns | ||||
tw3 | Minimum SYNC high pulse duration(1) | 25 | 35 | ns | ||||
td2 | SYNC rising edge to SCLK fall ignore delay time | 15 | 20 | ns | ||||
tw4 | LDAC pulse duration low | 20 | 30 | ns | ||||
td3 | SCLK falling edge to LDAC rising edge delay time | 10 | 20 | ns | ||||
tw5 | CLR minimum pulse duration low | 10 | 20 | ns | ||||
td4 | SCLK falling edge to LDAC falling edge delay time | 10 | 20 | ns | ||||
tv | SCLK rising edge to SDO valid time | 18 | 18 | ns | ||||
td5 | SCLK falling edge to SYNC rising edge delay time | 5 | 10 | ns | ||||
td6 | SYNC rising edge to SCLK rising edge delay time | 5 | 10 | ns | ||||
td7 | SYNC rising edge to LDAC or CLR falling edge delay time | 20 | 40 | ns | ||||
t19 | CLR pulse activation time | 20 | 20 | ns | ||||
t20 | Successive DAC Update | 2.4 | 2.4 | µs |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC load 5 kΩ//200 pF |
DAC code = mid-scale code |
VDD = 2.7 V, REFIN = 2.5 V |
REFIN = 2.5 V, DAC code = mid-scale code |
VDD = 2.7 V, REFIN = 2.5 V |
REFIN = 2.5 V, All channels active with full-scale code, DAC unloaded |
DAC code transition from 8000h to 7FFFh |
From code 512d to 65024d, Typical channel shown |
DAC unloaded, All channels to mid-scale | ||
DAC code transition from 7FFFh to 8000h |
From code 65024d to 512d, Typical channel shown |
DAC unloaded |
DAC unloaded, DAC code mid-scale, Typical channel shown | ||
DAC unloaded, Typical channel shown |
DAC in power down mode (1 kΩ-GND) |
VDD = 5.0 + 1 VPP (Sinusoid), REFIN = 2.5 V, DAC code full-scale, Typical channel shown |
DAC unloaded, DAC code mid-scale, Typical channel shown | ||
The DAC80004, DAC70004, and DAC60004 are quad-channel, 16-bit, voltage-output DACs with internal reference buffers and output buffers. Each channel consists of an R-2R ladder configuration with the 4 MSBs segmented, followed by an operational amplifier, as shown in Figure 51. The DACx0004 devices have a constant impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders. With the production trim process these devices have excellent dc accuracy and ac performance.
The input coding to the DACx0004 is straight binary, so the ideal output voltage is given by Equation 1:
Where:
N = resolution in bits; either 16 (DAC80004), 14 (DAC70004) or 12 (DAC60004)
DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2N –1
REFIN = DAC reference voltage
The DACx0004 output buffer amplifier is capable of generating near rail-to-rail voltages on its output, giving a maximum output range of 0 V to REFIN. It is capable of driving a load of 5 kΩ in parallel with 2 nF to GND. The typical slew rate of this amplifier while driving no load is 1.5 V/µs, with a full-scale settling time of 8 µs to 1 LSB of the final value as shown in Figure 43 and Figure 44. The current consumption of the amplifier (unloaded) is 1 mA/channel (typical). The DACx0004 output amplifier also implements a short circuit current limiting circuit. The default value of short circuit limit is 40 mA, however this can be reduced to 30 mA using dedicated bits (1 per channel) via SPI command 1010 (see Table 2).
The DACx0004 requires an external reference to operate. The reference input pin has the following input range:
2.2 V to (VDD – 0.2) for 2.7 V ≤ VDD ≤ 4.5 V
2.2 V to VDD for 4.5 V ≤ VDD ≤ 5.5 V
The DACx0004 contains a dedicated reference buffer for each DAC channel. The REFIN pin drives the input of these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin. This simplifies the external reference drive circuit for the device.
The DACx0004 contain a power-on-reset circuit that controls the output voltage during power up. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1).
The DAC power-on reset code for all of the channels depends on the state of the POR pin at power up (see Pin Configuration and Functions).
Each DAC channel remains that way until a valid load command is written to it. All device registers are reset at power up as shown in Table 1.
REGISTER NAME | DACx0004 - POWER-ON RESET VALUE |
---|---|
TSSOP-/VSON-14 | |
DAC latches (per channel) | If POR pin = '0' then Zero Scale else Mid scale |
DAC buffers (per channel) | If POR pin= '0' then Zero Scale else Mid scale |
Power down (per channel) | 00 – Normal mode |
Clear mode | 00 – Clear to Zero |
Ignore LDAC (per channel) | 0000 – Do not ignore |
Daisy chain | 0 – Daisy chain disabled, DAC update at 32nd SCLK falling edge |
Short circuit limit (per channel) | 0000 – all DACs 40 mA |
When the device powers up, an IPOR circuit sets the device in default mode as shown in Table 1. The IPOR circuit requires specific VDD levels, as indicated in Figure 52, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms. When VDD drops below 2.4 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power supply conditions. In this case, In this case a power-down reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur.
The DACx0004 devices have a 4-wire serial interface: SYNC, SCLK, SDIN, and SDO (see Pin Configuration and Functions). The serial interface (3-wire and 4-wire) is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs and it operates up to 50 MHz. See the Write Mode Stand-Alone Timing and Write Mode Daisy-Chain Timing diagrams (see Figure 1 and Figure 2) for examples of typical write and read sequences. The input shift register is 32 bits wide.
The serial clock SCLK can be a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin (TSSOP-14 and VSON-14 packages) is in a Hi-Z state. The device internal registers are updated from the shift register on the 32nd falling edge of SCLK.
For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC register updates on the 32nd SCLK falling edge. However, if SYNC is brought high before the 32nd SCLK falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 53).
The READ command is used to start read-back operation. However, before read-back operation can be initiated, the SDO pin must be enabled by setting the DSDO bit to '1'; this bit is disabled by default. Read-back operation is then started by executing a READ command (R/W bit = '1', see Table 3). Bits C3 to C0 select the register to be read. The remaining data in the command are don’t care bits. During the next SPI operation, the data appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP (No Operation) command (1110) can be used to clock out the data from the selected register on SDO. Multiple registers can be read if multiple READ commands are issued (see Figure 54).
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together (see Figure 55). Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial interface lines. The daisy-chain feature can be enabled by writing a logic '1' to the DSDO bit (see Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0.
The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI shift register when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appear on the SDO line. The data bits are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed (see Figure 2). Each device in the system requires 32 clock pulses. Therefore, the total number of clock cycles must equal 32 × N, where N is the total number of DACx0004s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI shift registers to the device internal registers for each device in the daisy-chain and prevents any further data from being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the data.
For daisy-chain operation, the SYNC line stays low for at least 32 × N SCLK cycles, where N is the number of DACx0004s in the daisy chain. If SYNC is brought high before a multiple 32 SCLKs, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56).
The SPI shift register is 32 bits wide, as shown in Table 2. The shift register command mapping is shown in Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from MSB (D19) to LSB (D4 - 16 bits, D6 - 14 bits, D8 - 12 bits).
D31 | D30 | D29 | D28 | D27-D24 | D23-D20 | D19-D04 | D03-D00 |
---|---|---|---|---|---|---|---|
Don't Cares | R/W | Command Bits | Channel Address Bits | 16/14/12-Bit DAC Data left alligned/Power Down Bits/Device Ready bit | Mode Bits |
D31 - D28 | D27 - D24 | D23 - D20 | D19 - D16 | D15 - D12 | D11 - D08 | D07 - D04 | D03 - D00 | Commands | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
X | W/R | 0 | 0 | 0 | 0 | Channel Address | DAC Data | DAC Data | DAC Data | DAC Data | X | Write to buffer n | ||||||
X | W | 0 | 0 | 0 | 1 | Channel Address | X | X | X | X | X | Update DAC n | ||||||
X | W | 0 | 0 | 1 | 0 | Channel Address | DAC Data | DAC Data | DAC Data | DAC Data | X | Write to buffer n and update all DACs (Software LDAC) | ||||||
X | W | 0 | 0 | 1 | 1 | Channel Address | DAC Data | DAC Data | DAC Data | DAC Data | X | Write to buffer and update DAC n | ||||||
X | W/R | 0 | 1 | 0 | 0 | X | X | X | X | PD1 | PD0 | Ch-D | Ch-C | Ch-B | Ch-A | Power up/down DAC n | ||
X | W/R | 0 | 1 | 0 | 1 | X | X | X | X | X | X | X | CM1 | CM0 | Clear mode register | |||
X | W/R | 0 | 1 | 1 | 0 | X | X | X | X | X | Ch-D | Ch-C | Ch-B | Ch-A | LDAC register | |||
X | W | 0 | 1 | 1 | 1 | X | X | X | X | X | X | Software reset | ||||||
X | W/R | 1 | 0 | 0 | 0 | X | X | X | X | X | X | DSD0 | X | Disable SDO register | ||||
X | X | 1 | 0 | 0 | 1 | X | X | X | X | X | X | Reserved | ||||||
X | W/R | 1 | 0 | 1 | 0 | X | X | X | X | X | Ch-D | Ch-C | Ch-B | Ch-A | Short circuit limit register | |||
X | W | 1 | 0 | 1 | 1 | X | X | X | X | X | X | Software clear | ||||||
X | X | 1 | 1 | 0 | 0 | X | X | X | X | X | X | Reserved | ||||||
X | R | 1 | 1 | 0 | 1 | X | X | X | X | X | DRDY | X | Status register | |||||
X | W | 1 | 1 | 1 | 0 | X | X | X | X | X | X | No operation (NOP) | ||||||
X | X | 1 | 1 | 1 | 1 | X | X | X | X | X | X | Reserved |
CHANNEL ADDRESS BITS | DESCRIPTION | |||
---|---|---|---|---|
D23 | D22 | D21 | D20 | |
0 | 0 | 0 | 0 | Select channel A |
0 | 0 | 0 | 1 | Select channel B |
0 | 0 | 1 | 0 | Select channel C |
0 | 0 | 1 | 1 | Select channel D |
1 | 1 | 1 | 1 | Select all channel |
The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24 and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09), PD0 (D08).
POWER DOWN BITS | DESCRIPTION | |
---|---|---|
D09 | D08 | |
0 | 0 | Normal operation/power up selected channel(s) (Default) |
0 | 1 | Power down selected channel(s) 1 kΩ-GND |
1 | 0 | Power down selected channel(s) 100 kΩ-GND |
1 | 1 | Power down selected channel(s) Hi-Z |
It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value.
The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC power-down circuitry is shown in Figure 57.
The CLR pin is an asynchronous input pin to the DAC. When activated, this falling edge sensitive pin clears the DAC buffers and the DAC latches to zero, mid, full or user programmed code depending on the clear mode register (see Table 6). The default setting for clear operation is clear to 0 V. The device exits clear mode on the 32nd falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately. Additionally, all DAC registers can also be cleared via SPI command 1011. Note that the clear mode bits determine the clear code for all the DACs upon clear operation.
The DACx0004 implement four different clear modes. These modes are accessed by setting command bits D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3). Based on the value of clear mode register (see Table 6), all of the DAC and the buffers are cleared to zero, mid, or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued.
The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24.
CLEAR MODE BITS | DESCRIPTION | |
---|---|---|
D01 | D00 | |
0 | 0 | All DACs clear to zero scale (default) |
0 | 1 | All DACs clear to mid scale |
1 | 0 | All DACs clear to full scale |
The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode.
In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then pulse the LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is pulsed low.
In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word (D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin.
See Table 7 for more information.
LDAC REGISTER BITS (D03 – D00) | DAC UPDATE |
---|---|
0 | Determined by LDAC pin (Default) |
1 | DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels see LDAC as 0 |
The DACx0004 implements a software reset feature. The software reset function uses command bits D28 – D24 (see Table 3). Table 1 shows the reset values for different registers.
The DACx0004 output amplifier has a default short circuit limit of 40 mA. However, this limit can be reduced to 30 mA by using command 1010 on bits D28 – D24 and selecting channel(s) (D03 – D00). Please note that DACx0004 has a dedicated bit per channel, this allows the user to set different short circuit limit for different DAC output channels.
SHORT CIRCUIT LIMIT REGISTER BITS (D03 – D00) | DAC SHORT CIRCUIT LIMIT |
---|---|
0 | DAC output short circuit limit = 40 mA (Default) |
1 | DAC output short circuit limit = 30 mA |
The DACx0004 implements a read-only status register (see Table 3). This register can be read by using command 1101 on bits D28 – D24, followed by a NOP command.
Logic ‘1’ on bit D04 indicates that the device is ready to be used. This feature is useful to check if the device is ready to accept commands after power up.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This design requires two channels of the DACx0004 to generate a bipolar output. The design is very flexible and allows for many different configurations. Typically, one channel is used to finely control the output, while the other is used to offset the output. The direction of the offset depends on which channel is used as an offset. DACPOS provides a positive offset and DACNEG has a negative offset.
The output of each DAC can be modified via the digital interface and the gain of each output can be modified independently by changing the external resistors. In order for the gain of each offset to be independent, Equation 2 must be true.
The output voltage range, VOUT, is adjusted according to Equation 3. Keep in mind that Equation 3 is only true when Equation 2 is true.
Each DAC outputs a voltage from 0 to REFIN. As an example, if DACPOS gain is 1, DACNEG gain is 2 and RFB = 2 kΩ, then RPOS = 2 kΩ, RNEG = 1 kΩ and RA = 1 kΩ. With the correct digital implementation it gives the output an effective output range of ±15 V, with discrete 16-bit steps.
Figure 59 displays two different modes of operation. Mode 1 gains the output of DACNeg by a factor of 2 and maintains DACPOS at unity gain. Mode 2 reverses the gains of each stage to invert the system. These are just two examples of the types of outputs that can be achieved using this configuration.
The DACx0004 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD should be well-regulated and have low-noise. Switching power supplies and DC-DC converters often have high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. A 1 µF to 10 µF capacitor and 0.1 µF bypass capacitor is recommended in order to further minimize noise from the power supply. The current consumption on the VDD pin, the short-circuit current limit, and the load current for the device are listed in the Electrical Characteristics. The power supply must meet the aforementioned current requirements.
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As a general rule it is important to keep digital traces as far away from analog traces when possible.
The DACx0004 is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DACx0004, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND must be connected directly to an analog ground plane. This plane must be separate from the ground connection for the digital components until they were connected at the power-entry point of the system.
As with the GND connection, VDD should be connected to a 5 V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. It is recommended to have an additional 1 μF to 10 μF capacitor and 0.1 μF bypass capacitor. In some situations, additional bypassing may be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. In general it is always a good idea to maintain the digital signals away from analog signals.
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The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
DAC60004 | Click here | Click here | Click here | Click here | Click here |
DAC70004 | Click here | Click here | Click here | Click here | Click here |
DAC80004 | Click here | Click here | Click here | Click here | Click here |
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
DAC80004IPW Device Marking Addendum: Note that both DA80004 and XDC84 are valid Device Markings for the DAC80004IPW Orderable Device
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