SBAS721A December   2015  – January 2016 DAC60096

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DAC DC
    6. 6.6  Electrical Characteristics: Square-Wave Output
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics: DC Mode
    10. 6.10 Typical Characteristics: Toggle Mode
    11. 6.11 Typical Characteristics, General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converters (DACs)
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Reference Specifications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Toggle Mode
      2. 7.4.2 DC Mode
    5. 7.5 Programming
      1. 7.5.1 Frame Error Checking
    6. 7.6 Register Maps
      1. 7.6.1 8.5.1 BUFA Register (address = 0x0) [reset = 0x0000]
      2. 7.6.2 BUFB Register (address = 0x1) [reset = 0x0000]
      3. 7.6.3 CON Register (address = 0x4) [reset = 0x0555]
      4. 7.6.4 CRC Register (address = 0x5) [reset = 0xFFF]
      5. 7.6.5 PTR Register (address = 0x6) [reset = 0x0000]
      6. 7.6.6 SWR Register (address = 0x7) [reset = 0x0000]
      7. 7.6.7 PWRM Register (address = 0x6) [reset = 0xCAFE]
      8. 7.6.8 SDIV Register (address = 0x9) [reset = 0x0000]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-Supply Bypassing
        2. 8.2.2.2 Reference Input
        3. 8.2.2.3 TRIGG/Signal Conditioning
        4. 8.2.2.4 External Amplifier Selection
        5. 8.2.2.5 Unbuffered Settling Response
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Device Reset Options
      1. 9.1.1 Power-on-Reset (POR)
      2. 9.1.2 Hardware Reset
      3. 9.1.3 Software Reset
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Optimal Layout Example
      2. 10.2.2 Standard Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

ZEB Package
196-Ball NFBGA
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND D10, E10,
F1, F2, F5, F10,
G2, G5, G10, H2, H10,
J1, J2, J5, J10,
K10, L10		 GND Analog ground.
AVCC E1, E6, E7, E8, E9, E14,
F7, F8, J7, J8,
K1, K6, K7, K8, K9, K14		 PWR Positive analog supply voltage. (11.2 V to 12.6 V). A 100-nF bypass capacitor for each AVCC_n (n = G1, G2, G3, G4, G5, G6, G7, G8, S1, S2, S3 or S4) is required; place as close as possible to the pins.
AVSS B1, B6, B7, B8, B9, B14,
F6, F9, J6, J9,
N1, N6, N7, N8, N9, N14		 PWR Negative analog supply voltage. (-12.6V to -11.2V). A 100-nF bypass capacitor for each AVSS_n (n = G1, G2, G3, G4, G5, G6, G7, G8, S1, S2, S3 or S4) is required; place as close as possible to the pins.
CLEAR H5 I Asynchronous clear control input, active low. When CLEAR is low, all DACs are loaded with code 000h. When CLEAR is high, all DACs return to normal operation
CS G4 I Serial data enable, active low. This input is the frame synchronization signal for the serial data.
DAC[1-13]_G1 A1, A2, A3, A4,
B2, B3, B4, C2, D2, D3,
E2, E3, E4		 O Subsystem 1 Regular DAC outputs: DAC group 1 and DAC group 2. Each DAC subsystem can be controlled independently through the serial interface.
DAC[14-26]_G2 A5, A6, A7, B5,
C3, C4, C5,
D4, D5, E5, E11		 O
DAC[1-13]_G3 A8, A9, A10, A11,
B10, B11, C10, C11,
D11, E12, F12, G12, G13		 O Subsystem 2 Regular DAC outputs: DAC group 3 and DAC group 4. Each DAC subsystem can be controlled independently through the serial interface.
DAC[14-24]_G4 A12, A13, A14,
B12, B13, C12, C13,
D12, D13, E13, F13		 O
DAC[3-13]_G5 H12, H13, J13, K13, L13,
M12, M13, N13,
P12, P13, P14		 O Subsystem 3 Regular DAC outputs: DAC group 5 and DAC group 6. Each DAC subsystem can be controlled independently through the serial interface.
DAC[14-26]_G6 J12, K12
L11, L12, M11, N11, N12,
P8, P9, P10, P11		 O
DAC[1-13]_G7 K4, K5, K11, L5,
M5, M10, N4, N5, N10,
P4, P5, P6, P7		 O Subsystem 4 Regular DAC outputs: DAC group 7 and DAC group 8. Each DAC subsystem can be controlled independently through the serial interface.
DAC[14-26]_G8 K2, K3, L2, L3, L4,
M2, M3, M4, N2, N3,
P1, P2, P3		 O
DGND G6, G9, H6, H9 GND Digital ground. Ground reference point for all digital circuitry on the device.
DNC F11, F14, G11
H11, J11, J14		 — Reserved for factory use. For proper operation, do not connect.
DVDD G7, G8, H7, H8 PWR Digital supply voltage. (3 V to 5.5 V). A 100-nF bypass capacitor is required; place as close as possible to the pins.
LDAC J4 I Synchronous DAC load control input, active low. When LDAC is low, the DAC outputs are updated immediately after a register write. If left high during DAC register updates, bringing LDAC low causes all DAC outputs to update simultaneously.
RESET F4 I Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.
REFGND1 H1 GND Reference ground. Ground reference point for REF1. REFGND1 should be star connected at the system GND source and not connected to the GND plane for best performance.
REFGND2 H14 GND Reference ground. Ground reference point for REF2. REFGND2 should be star connected at the system GND source and not connected to the GND plane for best performance.
SCLK H4 I Serial interface clock.
SDI H3 I Serial interface data input. Data are clocked into the input shift register on each rising edge of SCLK.
SDO G3 O Serial interface data output. The SDO pin is in high impedance when CS is high. Data can be clocked out of the input shift register on either rising or falling edges of SCLK as specified by PHAINV in the CON register.
STATS F3 O DAC output status indicator. Identifies which of the two DAC data registers is active.
REF1 G1 I Input voltage reference pin 1 (2.5 V). A 100-nF bypass capacitor between this pin and REFGND1 is required.
REF2 G14 I Input voltage reference pin 2 (2.5 V). A 100-nF bypass capacitor between this pin and REFGND2 is required.
TRIGG J3 I Trigger input signal. Enables all DAC outputs to toggle between the two DAC data registers associated with each DAC. This functionality enables the device to operate as a square-wave generator. The DAC registers are prepared for toggle mode operation on a TRIGG rising edge and the outputs are toggled on each following TRIGG falling edge.
VREFH D1, D6, D7, D8, D9, D14,
L1, L6, L7, L8, L9, L14		 O Compensation capacitor connection for the internal 10.5 V reference voltage. A 100-nF bypass capacitor for each VREFH_n (n = G1, G2, G3, G4, G5, G6, G7 or G8) is required; place as close as possible to the pins.
VREFL C1, C6, C7, C8, C9, C14,
M1, M6, M7, M8, M9, M14		 O Compensation capacitor connection for the internal -10.5 V reference voltage. A 100-nF bypass capacitor for each VREFL_n (n = G1, G2, G3, G4, G5, G6, G7 or G8) is required; place as close as possible to the pins.