SBAS793A
November 2019 – April 2020
DAC60502
,
DAC70502
,
DAC80502
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Functional Block Diagram
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements : SPI Mode
7.7
Timing Requirements : I2C Standard Mode
7.8
Timing Requirements : I2C Fast Mode
7.9
Timing Requirements : I2C Fast-Mode Plus
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital-to-Analog Converter (DAC) Architecture
8.3.1.1
DAC Transfer Function
8.3.1.2
DAC Register Structure
8.3.1.3
Output Amplifier
8.3.2
Internal Reference
8.3.2.1
Solder Heat Reflow
8.3.3
Power-On Reset (POR)
8.3.4
Software Reset
8.4
Device Functional Modes
8.4.1
Power-Down Mode
8.5
Programming
8.5.1
Serial Interface
8.5.1.1
SPI Mode
8.5.1.1.1
SYNC Interrupt
8.5.1.2
I2C Mode
8.5.1.2.1
F/S Mode Protocol
8.5.1.2.2
DACx0502 I2C Update Sequence
8.5.1.2.2.1
DACx0502 Address Byte
8.5.1.2.2.2
DACx0502 Command Byte
8.5.1.2.2.3
DACx0502 Data Byte (MSDB and LSDB)
8.5.1.2.3
DACx0502 I2C Read Sequence
8.6
Register Maps
8.6.1
Registers
8.6.1.1
NOOP Register (offset = 0h) [reset = 0000h]
Table 9.
NOOP Register Field Descriptions
8.6.1.2
DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for DAC60502]
Table 10.
DEVID Register Field Descriptions
8.6.1.3
SYNC Register (offset = 2h) [reset = 0300h]
Table 11.
SYNC Register Field Descriptions
8.6.1.4
CONFIG Register (offset = 3h) [reset = 0000h]
Table 12.
CONFIG Register Field Descriptions
8.6.1.5
GAIN Register (offset = 4h) [reset = 0003h]
Table 13.
GAIN Register Field Descriptions
8.6.1.6
TRIGGER Register (offset = 5h) [reset = 0000h]
Table 14.
TRIGGER Register Field Descriptions
8.6.1.7
BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Table 15.
BRDCAST Register Field Descriptions
8.6.1.8
STATUS Register (offset = 7h) [reset = 0000h]
Table 16.
STATUS Register Field Descriptions
8.6.1.9
DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Table 17.
DAC-A Data Register Field Descriptions (8h)
Table 18.
DAC-B Data Register Field Descriptions (9h)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
System Examples
9.3.1
SPI Connection to a Processor
9.3.2
I2C Interface Connection to a Processor
9.4
What To Do and What Not To Do
9.4.1
What To Do
9.4.2
What Not To Do
9.5
Initialization Setup
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Related Links
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRX|10
MPSS105A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbas793a_oa
sbas793a_pm
9.4.2
What Not To Do
Do not use an external reference when the internal reference is on. There is no current limit on the internal reference.