SLASEH4 November 2023 DAC61401 , DAC81401
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The DAC double-buffered architecture enables data updates without disturbing the analog output. Data updates are performed asynchronously. In the update mode, a minimum wait time of 2.4 μs (tDACWAIT) is required between DAC output updates.
During update mode, a DAC data register write results in an immediate update of the DAC active register and the DAC output on a SYNC rising edge. The wait time is governed by SYNC timing (Figure 5-3).