SLASEH3A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 Stand-Alone Operation

A serial interface access cycle is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDIN data are clocked on SCLK falling edges. A regular serial interface access cycle is 24 bits long with error checking disabled and 32 bits long with error checking enabled. Therefore, the SYNC pin must stay low for at least 24 or 32 SCLK falling edges. The access cycle ends when the SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle contains more than the minimum clock edges, only the first 24 or 32 bits are used by the device. When SYNC is high, the SCLK and SDIN signals are blocked, and SDO is in a Hi-Z state.

Table 8-2 describes the format for an error-checking-disabled access cycle (24-bits long). The first byte input to SDIN is the instruction cycle. The instruction cycle identifies the request as a read or write command and the 6-bit address that is to be accessed. The last 16 bits in the cycle form the data cycle.

Table 8-2 Serial Interface Access Cycle
BITFIELDDESCRIPTION
23RWIdentifies the communication as a read or write command to the address register:
R/W = 0 sets a write operation.
R/W = 1 sets a read operation
22xDon't care bit
21-16A[5:0]Register address — specifies the register to be accessed during the read or write operation
15-0DI[15:0]Data cycle bits:
If a write command, the data cycle bits are the values to be written to the register with address A[5:0]
If a read command, the data cycle bits are don't care values

Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data. The output data format is shown in Table 8-3. Data are clocked out on the SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit.

Table 8-3 SDO Output Access Cycle
BITFIELDDESCRIPTION
23RWEcho RW from previous access cycle
22xEcho bit 22 from previous access cycle
21-16A[5:0]Echo address from previous access cycle
15-0DO[15:0]Readback data requested on previous access cycle