SLASEO0B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 Design Requirements

Designing biasing circuits that are made to match both types of MZM technologies (LiNbO3 and InP) requires high voltage and current ranges as shown in Table 9-1. The Optical Internetworking Forum (OIF) recommends four differential IQ bias and two differential phase bias inputs, as shown in Figure 9-1. This differential signaling scheme helps in minimizing the crosstalk and noise between channels, which may otherwise result in a complicated bias control algorithm. While an ideal dither tone should be a sine wave, generating a sine wave can be cumbersome in a largely digital circuit domain. A square wave is relatively easier to generate through digital circuits, and can also be used, provided that the bandwidth of this dither signal is lower than the low cutoff frequency of the receiver (that is, 100 kHz or 1 MHz as per OIF). Passive RC filters with cutoff frequency lower than 100 kHz can be used at the DAC output for LiNbO3 modulators, which have very small bias current requirement. For InP modulators that are mainly used with optical modules, typically requiring a receiver low cutoff frequency of MHz, choose RC values so that the power dissipation across the resistors is small.

For smooth detection of the dither signal at the MZM output, use two orthogonal dither frequency sources for the I and Q arms. The amplitude of the dither waveform is typically 0.5% to 2.5% of the dc bias voltage, which is mainly governed by the design implementation.

Table 9-1 Requirements of MZM Biasing Circuit
PARAMETER VALUE
DC range Up to ±18 V
Dither amplitude 40 mV to 500 mV
Dither frequency 100 Hz to 100 kHz
Dither shape Sine or square
Bias current Up to 25 mA (for InP MZM)
Number of dither frequencies 2
Output type Differential (6 pairs)