SLASF73 April 2023 DAC63202W
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 0.5 | µs | ||
tHDSTA | Hold time after repeated start | 0.26 | µs | ||
tSUSTA | Repeated start setup time | 0.26 | µs | ||
tSUSTO | Stop condition setup time | 0.26 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 50 | ns | ||
tLOW | SCL clock low period | 0.5 | µs | ||
tHIGH | SCL clock high period | 0.26 | µs | ||
tF | Clock and data fall time | 120 | ns | ||
tR | Clock and data rise time | 120 | ns | ||
tVDDAT | Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF | 0.45 | µs | ||
tVDACK | Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF | 0.45 | µs |