SLASED6D April   2016  – December 2017 DAC60004 , DAC70004 , DAC80004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 DACx0004 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Amplifier
      2. 8.3.2 Reference Buffer
      3. 8.3.3 Power-On Reset
        1. 8.3.3.1 POR Pin Feature
        2. 8.3.3.2 Internal Power-On Reset (IPOR) Levels
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Stand-Alone Mode
          1. 8.4.1.1.1 SYNC Interrupt - Stand-Alone Mode
          2. 8.4.1.1.2 Read-Back Mode
        2. 8.4.1.2 Daisy-Chain Mode
          1. 8.4.1.2.1 SYNC Interrupt - Daisy-Chain Mode
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 DAC Power-Down Modes
      4. 8.4.4 CLR Pin Functionality and Software CLEAR Mode
        1. 8.4.4.1 DAC Clear Mode Registers
      5. 8.4.5 LDAC Pin Functionality
        1. 8.4.5.1 Software LDAC Mode Registers
      6. 8.4.6 Software Reset Mode
      7. 8.4.7 Output Short Circuit Limit Register
      8. 8.4.8 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output

DAC80004 DAC70004 DAC60004 app_schem_slase44.gif Figure 58. Asymmetric Bipolar Output Block Diagram

9.2.1 Design Requirements

This design requires two channels of the DACx0004 to generate a bipolar output. The design is very flexible and allows for many different configurations. Typically, one channel is used to finely control the output, while the other is used to offset the output. The direction of the offset depends on which channel is used as an offset. DACPOS provides a positive offset and DACNEG has a negative offset.

9.2.2 Detailed Design Procedure

The output of each DAC can be modified via the digital interface and the gain of each output can be modified independently by changing the external resistors. In order for the gain of each offset to be independent, Equation 2 must be true.

Equation 2. DAC80004 DAC70004 DAC60004 EQ2_lase44.gif

The output voltage range, VOUT, is adjusted according to Equation 3. Keep in mind that Equation 3 is only true when Equation 2 is true.

Equation 3. DAC80004 DAC70004 DAC60004 EQ3_lase44.gif

Each DAC outputs a voltage from 0 to REFIN. As an example, if DACPOS gain is 1, DACNEG gain is 2 and RFB = 2 kΩ, then RPOS = 2 kΩ, RNEG = 1 kΩ and RA = 1 kΩ. With the correct digital implementation it gives the output an effective output range of ±15 V, with discrete 16-bit steps.

9.2.3 Application Curve

Figure 59 displays two different modes of operation. Mode 1 gains the output of DACNeg by a factor of 2 and maintains DACPOS at unity gain. Mode 2 reverses the gains of each stage to invert the system. These are just two examples of the types of outputs that can be achieved using this configuration.

DAC80004 DAC70004 DAC60004 D059_slase44.gif Figure 59. Output Voltage vs Fine DAC Input Code