SBAS794E november   2018  – august 2023 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI Mode
    7. 7.7  Timing Requirements: I2C Standard Mode
    8. 7.8  Timing Requirements: I2C Fast Mode
    9. 7.9  Timing Requirements: I2C Fast-Mode Plus
    10. 7.10 Timing Diagrams
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 I2C Update Sequence
            1. 8.5.1.2.2.1 Address Byte
            2. 8.5.1.2.2.2 Command Byte
            3. 8.5.1.2.2.3 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 I2C Read Sequence
    6. 8.6 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C; all typical values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V, RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
STATIC PERFORMANCE
ResolutionDAC8050116Bits
DAC7050114
DAC6050112
INLIntegral nonlinearity(1)–11LSB
DNLDifferential nonlinearity(1)–11LSB
TUETotal unadjusted error(1)DAC80501, 
reference divider disabled (REF-DIV bit = 0)		–0.08–0.020.08%FSR
DAC80501, 
reference divider enabled (REF-DIV bit = 1)		–0.060.0250.06
DAC80501, DGS package 
reference divider enabled (REF-DIV bit = 1)
–0.070.0250.07
DAC70501, DAC60501–0.10.040.1
Zero code error(1)DAC loaded with zero scale code–1.50.51.5mV
Zero code error temperature coefficient(1)±2µV/°C
Offset error(1)–1.50.51.5mV
Offset error temperature coefficient (1)±2µV/°C
Gain error(1)DAC80501,
reference divider disabled (REF-DIV bit = 0)		–0.08–0.020.08%FSR
DAC80501,
reference divider enabled (REF-DIV bit = 1)		–0.060.0250.06
DAC80501, DGS package 
reference divider enabled (REF-DIV bit = 1)
–0.070.0250.07
DAC70501, DAC60501–0.10.040.1
Gain error temperature coefficient(1)±1ppm FSR/°C
Full-scale error(1)DAC80501, DAC loaded with full scale, reference divider disabled (REF-DIV bit = 0)–0.08–0.020.08%FSR
DAC80501, DAC loaded with full scale, reference divider enabled (REF-DIV bit = 1)–0.060.0250.06
DAC80501, DGS package 
reference divider enabled (REF-DIV bit = 1)
–0.070.0250.07
DAC70501, DAC60501–0.10.040.1
Full-scale error temperature coefficient(1)±2ppm FSR/°C
OUTPUT CHARACTERISTICS
VOOutput voltageBUFF-GAIN bit set to 1, REF-DIV bit set to 002 × VREFIOV
BUFF-GAIN bit set to 1, REF-DIV bit set to 10VREFIO
BUFF-GAIN bit set to 0, REF-DIV bit set to 100.5 × VREFIO
RLOADResistive load(2)VDD = 2.7 V0.25kΩ
VDD = 5.5 V0.5
CLOADCapacitive load(2)RLOAD = infinite2nF
RLOAD = 2 kΩ10
Load regulationDAC at midscale, –10 mA ≤ IOUT ≤ 10 mA80µV/mA
Short circuit currentFull scale output shorted to AGND30mA
Zero output shorted to VDD30
Output voltage headroomto VDD, DAC at full code, IOUT = 10 mA (sourcing)0.30.1V
Output voltage footroomto AGND, DAC at zero code, IOUT = 10 mA (sinking)0.3V
ZODC small signal output impedanceDAC at midscale0.1Ω
DAC at code 25610
DAC at code 6527910
Power supply rejection ratio (DC)DAC at midscale; VDD = 5 V ± 10%0.15mV/V
Output voltage drift vs timeTA = 35°C, VOUT = midscale, 1900 hr20ppm of FSR
VOLTAGE REFERENCE INPUT
ZVREFIOReference input impedance (VREFIO)100kΩ
CVREFIOReference input capacitance (VREFIO)5pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3)TA = 25°C2.49752.5025V
Output drift(3)DAC805015ppm/℃
DAC70501, DAC6050110
Output impedance(3)0.1Ω
Output noise(3)0.1 Hz to 10 Hz14µVPP
Output noise density(3)Measured at 10 kHz, reference load = 10 nF140nV/√ Hz
Load current(3)–0.5 mV < ΔVref < 0.5 mV ±5mA
Load regulation(3)Sourcing and sinking90µV/mA
Line regulation(3)20µV/V
Output voltage drift vs time(3)TA = 25°C, 1600 hr50ppm of FSR
Thermal hysteresis(3)1st cycle500µV
Additional cycle25µV
DYNAMIC PERFORMANCE
tsOutput voltage settling time(4)¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V5µs
10-mV settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V3
Slew rate(4)VDD = 5.5 V, VREFIO = 2.5 V2V/µs
Power on glitch magnitudeCLOAD = 50 pF200mV
VnOutput noise(4)0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V		14µVPP
100-kHz Bandwidth, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V		23µVrms
VnOutput noise densityMeasured at 1 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2 × (BUFF-GAIN bit = 1)		78nV/√ Hz
Measured at 10 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2 × (BUFF-GAIN bit = 1)		74
Measured at 1 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1 × (BUFF-GAIN bit = 0)		55
Measured at 10 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1 × (BUFF-GAIN bit = 0)		50
SFDRSpurious free dynamic range1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output70dB
THDTotal harmonic distortion1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output70dB
Power supply rejection ratio (ac)200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. (ac analysis)85dB
Code change glitch impulseMidcode ±1 LSB (including feedthrough)4nV-s
Code change glitch magnitudeMidcode ±1 LSB (including feedthrough)
gain = 1 × (BUFF-GAIN bit = 0)		7.5mV
Digital feedthroughAt SCLK = 1 MHz, DAC output at midscale4nV-s
DIGITAL INPUTS
Hysteresis voltage0.4V
Input current–55µA
Pin capacitancePer pin10pF
POWER REQUIREMENTS
IVDDCurrent flowing into VDDNormal mode, internal reference enabled, DAC at full scale, SPI static1.52.0mA
Normal mode, external reference = 2.5 V, DAC at full scale, SPI static11.4
DAC and Internal reference power-down15µA
IVREFIOCurrent flowing into VREFIO0-V to 5-V range, midscale code25µA
(1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12 bit, DAC output unloaded, performance under resistive and capacitance load conditions are specified by design and characterization, DAC output range ≥ 2.5 V.
(2) Not production tested.
(3) Characterized on 8-pin DQF package.
(4) Output buffer in gain = 2 × setting (BUFF-GAIN bit = 1).