SBAS793A November   2019  – April 2020 DAC60502 , DAC70502 , DAC80502

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements : SPI Mode
    7. 7.7  Timing Requirements : I2C Standard Mode
    8. 7.8  Timing Requirements : I2C Fast Mode
    9. 7.9  Timing Requirements : I2C Fast-Mode Plus
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 DACx0502 I2C Update Sequence
            1. 8.5.1.2.2.1 DACx0502 Address Byte
            2. 8.5.1.2.2.2 DACx0502 Command Byte
            3. 8.5.1.2.2.3 DACx0502 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 DACx0502 I2C Read Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Registers
        1. 8.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
          1. Table 9. NOOP Register Field Descriptions
        2. 8.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for DAC60502]
          1. Table 10. DEVID Register Field Descriptions
        3. 8.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
          1. Table 11. SYNC Register Field Descriptions
        4. 8.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
          1. Table 12. CONFIG Register Field Descriptions
        5. 8.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
          1. Table 13. GAIN Register Field Descriptions
        6. 8.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
          1. Table 14. TRIGGER Register Field Descriptions
        7. 8.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 15. BRDCAST Register Field Descriptions
        8. 8.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
          1. Table 16. STATUS Register Field Descriptions
        9. 8.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 17. DAC-A Data Register Field Descriptions (8h)
          2. Table 18. DAC-B Data Register Field Descriptions (9h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 SPI Connection to a Processor
      2. 9.3.2 I2C Interface Connection to a Processor
    4. 9.4 What To Do and What Not To Do
      1. 9.4.1 What To Do
      2. 9.4.2 What Not To Do
    5. 9.5 Initialization Setup
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC80502 16 Bits
DAC70502 14
DAC60502 12
INL Integral nonlinearity(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
TUE Total unadjusted error(1) –0.1 0.04 0.1 %FSR
Zero code error(1) DAC loaded with zero scale code –1.5 0.5 1.5 mV
Zero code error temperature coefficient(1) ±2 µV/°C
Offset error(1) –1.5 0.5 1.5 mV
Offset error temperature coefficient (1) ±2 µV/°C
Gain error(1) –0.1 0.04 0.1 %FSR
Gain error temperature coefficient(1) ±1 ppm FSR/°C
Full-scale error(1) –0.1 0.04 0.1 %FSR
Full-scale error temperature coefficient(1) ±2 ppm FSR/°C
OUTPUT CHARACTERISTICS
VO Output voltage BUFF-GAIN bit set to 1, REF-DIV bit set to 0 0 2 × VREFIO V
BUFF-GAIN bit set to 1, REF-DIV bit set to 1 0 VREFIO
BUFF-GAIN bit set to 0, REF-DIV bit set to 1 0 0.5 × VREFIO
RLOAD Resistive load(2) VDD = 2.7 V 0.25 kΩ
VDD = 5.5 V 0.5
CLOAD Capacitive load(2) RLOAD = infinite 2 nF
RLOAD = 2 kΩ 10
Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA 80 µV/mA
Short circuit current Full scale output shorted to AGND (per channel) 30 mA
Zero output shorted to VDD (per channel) 30
Output voltage headroom to VDD, DAC at full code, IOUT = 10 mA (sourcing) 0.3 0.1 V
Output voltage footroom to AGND, DAC at zero code, IOUT = 10 mA (sinking) 0.3 V
ZO DC small signal output impedance DAC at midscale 0.1 Ω
DAC at code 256 10
DAC at code 65279 10
Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10% 0.15 mV/V
Output voltage drift vs time TA = 35°C, VOUT = midscale, 1900 hr 20 ppm of FSR
VOLTAGE REFERENCE INPUT
ZVREFIO Reference input impedance (VREFIO) 100 kΩ
CVREFIO Reference input capacitance (VREFIO) 5 pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy) TA = 25°C 2.4975 2.5025 V
Output drift DAC80502 5 ppm/℃
DAC70502, DAC60502 10
Output impedance 0.1 Ω
Output noise 0.1 Hz to 10 Hz 14 µVPP
Output noise density Measured at 10 kHz, reference load = 10 nF 140 nV/√Hz
Load current ±5 mA
Load regulation Sourcing and sinking 90 µV/mA
Line regulation 20 µV/V
Output voltage drift vs time TA = 35°C, 1900 hr 20 µV
Thermal hysteresis 1st cycle 480 ppm
Additional cycle 25 ppm
DYNAMIC PERFORMANCE
ts Output voltage settling time(3) ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V 5 µs
10-mV settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V 3
Slew rate(3) VDD = 5.5 V, VREFIO = 2.5 V 2 V/µs
Power on glitch magnitude CLOAD = 50 pF 200 mV
Vn Output noise(3) 0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V		 14 µVPP
100-kHz Bandwidth, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V		 23 µVrms
Vn Output noise density Measured at 1 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)		 78 nV/√Hz
Measured at 10 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)		 74
Measured at 1 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)		 55
Measured at 10 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)		 50
SFDR Spurious free dynamic range 1-kHz sinusiod at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output 70 dB
THD Total harmonic distortion 1-kHz sinusiod at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output 70 dB
Power supply rejection ratio (ac) 200-mV, 50-Hz to 60-Hz sine wave on VDD, DAC at midscale. 85 dB
Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4 nV-s
Code change glitch magnitude Midcode ±1 LSB (including feedthrough)
gain = 1X (BUFF-GAIN bit = 0)		 7.5 mV
Channel to channel ac crosstalk Full scale swing on adjacent channel, measured channel at midscale 4 nV-s
Channel to channel dc crosstalk Full scale swing on adjacent channel, measured channel at midscale 1 LSB
Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 4 nV-s
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input current –5 5 µA
Pin capacitance Per pin 10 pF
POWER
IVDD Current flowing into VDD Normal mode, internal reference enabled, all DACs at full scale, SPI static 1.9 2.6 mA
Normal mode, external reference = 2.5 V, all DACs at full scale, SPI static 1.5 1.9
All DACs and Internal reference power-down 15 µA
IVREFIO Current flowing into VREFIO 0-V to 5-V range, midscale code 25 µA
(1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization, DAC output range ≥ 2.5 V.
(2) Not production tested.
(3) Output buffer in gain = 2X setting (BUFF-GAIN bit = 1).