SLASEO0B
July 2018 – June 2021
DAC61416
,
DAC71416
,
DAC81416
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Timing Diagrams
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital-to-Analog Converter (DAC) Architecture
8.3.1.1
DAC Transfer Function
8.3.1.2
DAC Register Structure
8.3.1.2.1
DAC Register Synchronous and Asynchronous Updates
8.3.1.2.2
Broadcast DAC Register
8.3.1.2.3
Clear DAC Operation
8.3.2
Internal Reference
8.3.3
Device Reset Options
8.3.3.1
Power-on-Reset (POR)
8.3.3.2
Hardware Reset
8.3.3.3
Software Reset
8.3.4
Thermal Protection
8.3.4.1
Analog Temperature Sensor: TEMPOUT Pin
8.3.4.2
Thermal Shutdown
8.4
Device Functional Modes
8.4.1
Toggle Mode
8.4.2
Differential Mode
8.4.3
Power-Down Mode
8.5
Programming
8.5.1
Stand-Alone Operation
8.5.1.1
Streaming Mode Operation
8.5.2
Daisy-Chain Operation
8.5.3
Frame Error Checking
8.6
Register Maps
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHA|40
MPQF135D
Thermal pad, mechanical data (Package|Pins)
RHA|40
QFND650
Orderable Information
slaseo0b_oa
slaseo0b_pm
8.2
Functional Block Diagram