SLASEO0B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Toggle Mode

Each DAC in the device can be independently configured to operate in toggle mode. A DAC channel in toggle mode incorporates two DAC registers (Register A and Register B) and can be set to switch repetitively between these two values. The DACx1416 toggle mode operation can be configured to introduce a dither signal to the DAC output, to generate a periodic signal or to implement ON/OFF signaling, among some examples.

To update the toggle registers the following sequence should be followed:

  1. Set DAC channel in synchronous mode and disable toggle mode for that channel
  2. Write the desired Register A value to the DAC data register
  3. Issue a DAC trigger signal to load Register A
  4. Write the desired Register B value to the DAC data register
  5. Enable toggle mode to load Register B

Once both registers are loaded with data, any of the three TOGGLE[2:0] pins can be used to switch those DACs configured for toggle operation back and forth between the contents of their two DAC specific registers by using an external clock or logic signal. A TOGGLE pin logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. The three TOGGLE[2:0] pins give the DACx1416 the option to operate with up to three toggle rates.

Additionally, the device can be configured for software controlled toggle operation by setting the SOFTTOGGLE-EN bit. In this mode, any of the three AB-TOG[2:0] bits can be used as a toggle control signal. Setting the AB-TOG bit to 1 enables Register B and clearing it to 0 enables Register A.