SLAS767B June 2011 – March 2015 DAC7551-Q1
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VDD | I | Analog voltage supply input |
2 | VREFH | I | Positive reference voltage input |
3 | VREFL | I | Negative reference voltage input |
4 | VFB | I | DAC amplifier sense input. |
5 | VOUT | O | Analog output voltage from DAC |
6 | GND | — | Ground. |
7 | CLR | I | Asynchronous input to clear the DAC registers. When the CLR pin is low, the DAC register is set to 000h and the output voltage to 0 V. |
8 | SYNC | I | Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7551-Q1 device. |
9 | SCLK | I | Serial clock input |
10 | SDIN | I | Serial data input |
11 | SDO | O | Serial data output |
12 | IOVDD | I | I/O voltage supply input |