SLAS950A May 2013 – June 2015 DAC7562-Q1 , DAC7563-Q1 , DAC8162-Q1 , DAC8163-Q1 , DAC8562-Q1 , DAC8563-Q1
PRODUCTION DATA.
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 (DACxx6x-Q1) devices are low-power, voltage-output, dual-channel, 12-, 14-, and 16-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin.
These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile three-wire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACxx62-Q1 devices incorporate a power-on-reset circuit that ensures the DAC output powers up and remains at zero scale until a valid code is written to the device, whereas the DACxx63-Q1 devices similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 550 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment.
The DACxx62-Q1 devices are drop-in and function-compatible with each device in this family, as are the DACxx63-Q1 devices. The entire family is available in a 10-pin VSSOP-10 (DGS) package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC7562-Q1 | VSSOP (10) | 3.00 mm × 3.00 mm |
DAC7563-Q1 | ||
DAC8162-Q1 | ||
DAC8163-Q1 | ||
DAC8562-Q1 | ||
DAC8563-Q1 |
Changes from * Revision (May 2013) to A Revision
PART NUMBER | RESOLUTION | MAXIMUM RELATIVE ACCURACY (LSB) | MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) | MAXIMUM REFERENCE DRIFT (ppm/°C) | RESET TO |
---|---|---|---|---|---|
DAC7562-Q1 | 12-bit | ±0.75 | ±0.25 | 10 | Zero |
DAC7563-Q1 | Mid-scale | ||||
DAC8162-Q1 | 14-bit | ±3 | ±0.5 | 10 | Zero |
DAC8163-Q1 | Mid-scale | ||||
DAC8562-Q1 | 16-bit | ±12 | ±1 | 10 | Zero |
DAC8563-Q1 | Mid-scale |
PIN | DESCRIPTION | |
---|---|---|
NAME | NO. | |
AVDD | 9 | Power-supply input, 2.7 V to 5.5 V |
CLR | 5 | Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale (DACxx62-Q1) or mid-scale (DACxx63-Q1) is loaded to all input and DAC registers. This sets the DAC output voltages accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. |
DIN | 8 | Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-trigger logic input |
GND | 3 | Ground reference point for all circuitry on the device |
LDAC | 4 | In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device. In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. |
SCLK | 7 | Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input |
SYNC | 6 | Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x-Q1, DAC816x-Q1, DAC856x-Q1. Schmitt-trigger logic input |
VOUTA | 1 | Analog output voltage from DAC-A |
VOUTB | 2 | Analog output voltage from DAC-B |
VREFIN/VREFOUT | 10 | Bidirectional voltage reference pin. If internal reference is used, 2.5-V output. |