SLASF62 June 2024 DAC80516
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
Each output channel in the DAC80516 consists of an R-2R ladder architecture followed by an output buffer amplifier. Figure 6-1 shows a block diagram of the DAC architecture.
After a reset event, all the DAC registers are set to zero-code, the DAC output amplifiers are powered down, and the DAC outputs are clamped to GND. Each DAC output can be independently enabled or disabled through software by writing to the appropriate bit of the PWDWN register. When disabled, the DAC output is clamped to ground via a pull-down resistor.