SLASF62 June   2024 DAC80516

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUY|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.12 Typical Characteristics

at TJ = 25°C, AVDD = 5.5V, VIO = 5.5V, internal reference = 2.5V, gain = 2, DAC outputs unloaded (unless otherwise noted)

DAC80516 Integral Nonlinearity vs Digital Input Code
 
Figure 5-3 Integral Nonlinearity vs Digital Input Code
DAC80516 Integral Nonlinearity vs Temperature
 
Figure 5-5 Integral Nonlinearity vs Temperature
DAC80516 Offset Error vs Temperature
 
Figure 5-7 Offset Error vs Temperature
DAC80516 Integral Nonlinearity vs Supply Voltage
 
Figure 5-9 Integral Nonlinearity vs Supply Voltage
DAC80516 Offset Error vs Supply Voltage
 
Figure 5-11 Offset Error vs Supply Voltage
DAC80516 Supply Current With External Reference vs Digital Input Code
Gain = 2, external reference = 2.5V
Figure 5-13 Supply Current With External Reference vs Digital Input Code
DAC80516 Supply Current With External Reference vs Temperature
Gain = 2, external reference = 2.5V
Figure 5-15 Supply Current With External Reference vs Temperature
DAC80516 Supply Current With External Reference vs Supply Voltage
Gain = 1, external reference = 2.5V
Figure 5-17 Supply Current With External Reference vs Supply Voltage
DAC80516 Headroom vs Load Current
Gain = 1, AVDD = 2.7V
Figure 5-19 Headroom vs Load Current
DAC80516 Source and Sink Capability
Gain = 1
Figure 5-21 Source and Sink Capability
DAC80516 Full-Scale Settling Time, Rising Edge
 
Figure 5-23 Full-Scale Settling Time, Rising Edge
DAC80516 Glitch Impulse, Falling Edge
1LSB step
Figure 5-25 Glitch Impulse, Falling Edge
DAC80516 Power-On, Reset to Zero Scale
 
Figure 5-27 Power-On, Reset to Zero Scale
DAC80516 Channel-to-Channel DC Crosstalk
Measured DAC at midscale
Figure 5-29 Channel-to-Channel DC Crosstalk
DAC80516 DAC Output AC PSRR vs Frequency
DAC code at full scale, VDD = 5V + 200mVPP
 
Figure 5-31 DAC Output AC PSRR vs Frequency
DAC80516 DAC Output Noise With External Reference 0.1Hz to 10Hz
DAC code at midscale, gain = 2, external reference = 2.5V
Figure 5-33 DAC Output Noise With External Reference 0.1Hz to 10Hz
DAC80516 Internal Reference Noise Density vs Frequency
Figure 5-35 Internal Reference Noise Density vs Frequency
DAC80516 Differential Nonlinearity vs Digital Input Code
 
Figure 5-4 Differential Nonlinearity vs Digital Input Code
DAC80516 Differential Nonlinearity vs Temperature
 
Figure 5-6 Differential Nonlinearity vs Temperature
DAC80516 Zero-Scale Error vs Temperature
 
Figure 5-8 Zero-Scale Error vs Temperature
DAC80516 Differential Nonlinearity vs Supply Voltage
 
Figure 5-10 Differential Nonlinearity vs Supply Voltage
DAC80516 Zero-Scale Error vs Supply Voltage
 
Figure 5-12 Zero-Scale Error vs Supply Voltage
DAC80516 Supply Current With Internal Reference vs Digital Input Code
 
Figure 5-14 Supply Current With Internal Reference vs Digital Input Code
DAC80516 Supply Current With Internal Reference vs Temperature
 
Figure 5-16 Supply Current With Internal Reference vs Temperature
DAC80516 Supply Current With Internal Reference vs Supply Voltage
Gain = 1
Figure 5-18 Supply Current With Internal Reference vs Supply Voltage
DAC80516 Headroom vs Load Current
Gain = 2, AVDD = 5V
Figure 5-20 Headroom vs Load Current
DAC80516 Source and Sink Capability
Gain = 2
Figure 5-22 Source and Sink Capability
DAC80516 Full-Scale Settling Time, Falling Edge
 
Figure 5-24 Full-Scale Settling Time, Falling Edge
DAC80516 Glitch Impulse, Rising Edge
1LSB step
Figure 5-26 Glitch Impulse, Rising Edge
DAC80516 Clear to Zero Scale
 
Figure 5-28 Clear to Zero Scale
DAC80516 Clock Feedthrough
DAC code at midscale, SCLK = 1MHz
Figure 5-30 Clock Feedthrough
DAC80516 DAC Output Noise Density vs Frequency
DAC channel at midscale
Figure 5-32 DAC Output Noise Density vs Frequency
DAC80516 DAC Output Noise With Internal Reference 0.1Hz to 10Hz
DAC code at midscale
Figure 5-34 DAC Output Noise With Internal Reference 0.1Hz to 10Hz
DAC80516 Internal Reference Noise
 
Figure 5-36 Internal Reference Noise