SLASF62A June   2024  – November 2024 DAC80516

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUY|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.1 DAC Register Structure

The DAC produces output voltages proportional to a 16-bit input data code. Input data are written to the DAC data register in straight binary format for all output ranges. By writing to the DAC_GAIN register, the user can configure the maximum full-scale DAC output voltage as either 1 × VREF or 2 × VREF (maximum of 5V), where VREF is the internal or external reference input voltage. Section 7.1.5 shows that the gain settings can be configured for QUAD0 (OUT0 through OUT3), QUAD1 (OUT4 through OUT7), QUAD2 (OUT8 through OUT11) and QUAD3 (OUT12 through OUT15); all DAC channels in a QUAD group share the same gain settings.

Data written to the DAC data registers are initially stored in the DAC buffer registers. The transfer of data from the DAC buffer registers to the DAC active registers can be configured to happen immediately (asynchronous mode) or initiated by a DAC trigger signal (synchronous mode). When the DAC active registers are updated, the DAC output channels change to the new values.

By setting the corresponding BCAST_EN bits in the DAC_BCAST_EN register, each DAC can be configured to operate in broadcast mode. When a value is written to the BCAST_DAC_DATA register, this value is automatically stored in the buffer and active data registers of all DACs operating in broadcast mode.

Additionally, each DAC has a short circuit detection circuit. The DAC_STATUS register indicates which DAC channels are presently in short-circuit condition. A global status bit (GDAC_SC_STS, in the STATUS register) is the logical OR of all the DAC_STATUS bits, which can be used to determine if there is at least one channel in the short circuit condition.