SLASF62 June 2024 DAC80516
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE (1) | ||||||
Resolution | 16 | Bits | ||||
INL | Relative accuracy | ±1 | ±2 | LSB | ||
DNL | Differential nonlinearity | ±0.6 | ±1 | LSB | ||
TUE | Total unadjusted error | DAC output range = 0V to 5V | ±0.06 | ±0.2 | %FSR | |
Offset error | Gain = 1 or 2 | ±0.75 | ±2 | mV | ||
Zero-code error | DAC register loaded with all zeroes | 0 | 0.5 | 1.5 | mV | |
Full-scale error | DAC register loaded at full-scale code (65535d) | ±0.05 | ±0.2 | %FSR | ||
Gain error | Gain = 1 or 2 | ±0.05 | ±0.15 | %FSR | ||
Offset error drift | ±2 | µV/°C | ||||
Zero-code error drift | ±2 | µV/°C | ||||
Full-scale error drift | ±2 | ppm FSR/°C | ||||
Gain error drift | ±1 | ppm FSR/°C | ||||
Output voltage drift over time | TJ = 25°C, DAC code = midscale, 1900 hours |
20 | ppm FSR | |||
OUTPUT CHARACTERISTICS | ||||||
Output voltage(2) | Gain = 2 | 0 | 2 × VREF | V | ||
Gain = 1 | 0 | VREF | ||||
Output voltage headroom | To AVDD (–50mA ≤ IOUT ≤ 50mA), DAC code = full-scale |
0.5 | V | |||
Load current | 50 | mA | ||||
Short-circuit current(3) | Full-scale output shorted to GND | 75 | mA | |||
Zero-scale output shorted to VDD | 75 | |||||
Capacitive load(4) | RLOAD = open | 0 | 2 | nF | ||
DC output impedance | DAC output at AVDD/2 | 0.08 | Ω | |||
DAC output at AVDD or GND | 10 | |||||
DYNAMIC PERFORMANCE | ||||||
Output voltage settling time | ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, AVDD = 5.5V, VREFIN = 2.5V, gain = 2 |
6 | µs | |||
Slew rate | AVDD = 5.5V, VREFIN = 2.5V | 1.7 | V/µs | |||
Power-on glitch magnitude | DAC code = zero scale | 25 | mV | |||
Output noise | 0.1Hz to 10Hz, DAC code = midscale | 12 | µVpp | |||
Output noise density | 1kHz, DAC code = midscale, AVDD = 5.5V, VREFIN = 2.5V |
65 | nV/Hz | |||
AC PSRR | DAC code = midscale, frequency = 60Hz, amplitude 200mVpp superimposed on AVDD | 80 | dB | |||
DC PSRR | DAC code = midscale, AVDD = 5V ±0.5V | 0.02 | mV/V | |||
Code change glitch impulse | 1LSB change around major carrier | 1 | nV-s | |||
Channel-to-channel ac crosstalk | DAC code = zero scale, full-scale swing on adjacent channel | 1 | nV-s | |||
Channel-to-channel dc crosstalk | Measured channel at zero scale, adjacent channel at full scale |
2 | µV | |||
Measured channel at zero scale, all other channels at full scale |
2 | |||||
Digital feedthrough | DAC code = midscale, fSCLK = 1MHz | 0.1 | nV-s | |||
Power-up time(5) | AVDD = 5.5V, VREFIN = 2.5V | 120 | µs | |||
EXTERNAL REFERENCE INPUT | ||||||
VREFIN | Reference input voltage range | Gain = 1 | 1 | VDD | V | |
Gain = 2 | 1 | AVDD/2 | ||||
Reference input current | VREFIN = 2.5V | 50 | µA | |||
Reference input impedance | 40 | 50 | 60 | kΩ | ||
Reference input capacitance | 5 | pF | ||||
INTERNAL REFERENCE | ||||||
VREFOUT | Reference output voltage range | TJ = 25°C | 2.4975 | 2.5025 | V | |
Reference output drift | 5 | 10 | ppm/°C | |||
Reference output impedance | 0.04 | Ω | ||||
Reference output noise | 0.1Hz to 10Hz | 10 | µVpp | |||
Reference output noise density | 10kHz, reference load = 10nF | 200 | nV/Hz | |||
Reference load current | ±10 | mA | ||||
Reference load regulation | Source and sink | 5 | µV/mA | |||
Reference line regulation | 100 | µV/V | ||||
Reference output drift over time | TJ = 25°C, 1900 hours | ±12 | µV | |||
Low-level output voltage | First cycle | ±125 | µV | |||
Additional cycle | ±25 | |||||
DIGITAL INPUTS AND OUTPUTS | ||||||
VIH | High-level input voltage, VIH | AVDD = 2.7V to 5.5V | 0.7 × VIO | V | ||
VIL | Low-level input voltage, VIL | AVDD = 2.7V to 5.5V | 0.3 × VIO | V | ||
Input current | ±2 | µA | ||||
Input pin capacitance | 8 | pF | ||||
VOH | High-level output voltage, VOH | IOH = 0.2mA | VIO - 0.2 | V | ||
VOL | Low-level output voltage, VOL | IOL = 0.2mA | 0.4 | V | ||
Output pin capacitance | 4 | pF | ||||
POWER REQUIREMENTS | ||||||
IAVDD | AVDD supply current | Active mode, internal reference enabled, DAC code = full-scale, SPI static | 10.5 | 13 | mA | |
Active mode, internal reference disabled, DAC code = full-scale, SPI static | 10 | 12.5 | ||||
AVDD supply current | Power-down mode | 6 | 10 | µA | ||
IVIO | VIO supply current | 2 | 3 | µA |