SLASEH4 November   2023 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 5.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 5.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 5.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 5.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 5.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3 Programmable Gain Output Buffer

The voltage output stage, as conceptualized in Figure 6-2, provides the voltage output according to the DAC code and the output range setting.

GUID-20230208-SS0I-6M0F-NL7M-PX83VSV0KK8J-low.svg Figure 6-2 DACx1401 Voltage Output

The DAC output range can be programmed. Table 6-1 shows the range and corresponding gain.

Table 6-1 Voltage Output Range vs Gain Setting
MODE VOLTAGE OUTPUT RANGE GAIN
Unipolar 5 V 2.0
6 V (20% overrange) 2.4
10 V 4.0
12 V (20% overrange) 4.8
20 V 8.0
24 V (20% overrange) 9.6
40 V 16.0
Bipolar ±5 V 4.0
±6 V (20% overrange) 4.8
±10 V 8.0
±12 V (20% overrange) 9.6
±20 V 16.0

The output voltage (VOUT) can be expressed as Equation 1 and Equation 2.

For unipolar output mode

Equation 1. V O U T = V R E F I O   ×   G A I N   ×   C O D E 2 N

For bipolar output mode

Equation 2. V O U T = V R E F I O × G A I N × C O D E 2 N - G A I N × V R E F I O 2

Where:

  • CODE is the decimal equivalent of the code loaded to the DAC register
  • N is the bits of resolution; 16-bits for DAC81401, 12-bits for DAC61401
  • VREFIO = 2.5 V is the reference voltage (internal or external)
  • GAIN is the gain factor assigned to each output voltage output range as shown in Table 6-1

The output amplifiers can drive up to ±15 mA with 1.5‑V supply headroom while maintaining the specified total unadjusted error (TUE) specification for the device. The output stage has short-circuit current protection that limits the output current to 40 mA. The device is designed to drive capacitive loads up to 2 nF with the CCOMP pin unconnected. For capacitive loads greater than 2 nF, an external compensation capacitor (470 pF typical) must be connected between the CCOMP and VOUT pins to keep the output voltage stable, but at the expense of reduced bandwidth and increased settling time. With the external compensation capacitor, the device is able to drive capacitive loads up to 1 µF (Section 5.5).