SLASEH4 November   2023 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 5.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 5.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 5.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 5.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 5.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.3 Frame Error Checking

If the device is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit in the SPICONFIG register.

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (100000111). When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding the data to the device. In all serial interface readback operations, the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.

Table 6-4 Error Checking Serial Interface Access Cycle
BIT FIELD DESCRIPTION
31 R/W Identifies the communication as a read or write command to the address register.
R/W = 0 sets a write operation.
R/W = 1 sets a read operation.
30 CRC-ERROR Reserved bit. Set to zero.
29:24 A[5:0] Register address. Specifies the register to be accessed during the read or write operation.
23:8 DI[15:0] Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address A[5:0].
If a read command, the data cycle bits are don't care values.
7:0 CRC 8-bit CRC polynomial.

The device decodes the 32-bit access cycle to compute the CRC remainder on SYNC rising edges. If no error exists, the CRC remainder is zero and data are accepted by the device.

A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.

If there is a CRC error, the CRC-ALM bit of the STATUS register is set to 1. The FAULT pin can be configured to monitor a CRC error by setting the CRCALM-EN bit in the SPICONFIG register.

Table 6-5 Write Operation Error Checking Cycle
BIT FIELD DESCRIPTION
31 R/W Echo R/W from previous access cycle (R/W = 0).
30 CRC-ERROR Returns a 1 when a CRC error is detected, otherwise returns a 0.
29:24 A[5:0] Echo address from previous access cycle.
23:8 DO[15:0] Echo data from previous access cycle.
7:0 CRC Calculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The error check result (CRC-ERROR bit) from the read command is output on the SDO pin.

As in the case of a write operation failing the CRC check, the CRC-ALM bit of the STATUS register is set to 1, and the FAULT pin, if configured for CRC alerts, is set low.

Table 6-6 Read Operation Error Checking Cycle
BIT FIELD DESCRIPTION
31 R/W Echo R/W from previous access cycle (R/W = 1).
30 CRC-ERROR Returns a 1 when a CRC error is detected, otherwise returns a 0.
29:24 A[5:0] Echo address from previous access cycle.
23:8 DO[15:0] Readback data requested on previous access cycle.
7:0 CRC Calculated CRC value of bits 31:8.