SLASEH4A November   2023  – December 2024 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - Write, IOVDD = 1.7V to 2.7V
    7. 5.7  Timing Requirements - Write, IOVDD = 2.7V to 5.5V
    8. 5.8  Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
    9. 5.9  Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
    10. 5.10 Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
    11. 5.11 Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 PW Package, 20-Pin TSSOP (Top View)
Figure 4-2 RTE Package, 16-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
PW (TSSOP) RTE (WQFN)
AVDD 5 6 Power Power supply
AVSS 3 5 Power Negative power supply
CCOMP 7 7 Input External compensation capacitor connection pin for VOUT.
Addition of the external capacitor (470pF, typical) improves the stability with high capacitive loads (up to 1μF) at the VOUT pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
FAULT 12 11 Output FAULT pin. Open drain output. External 10kΩ pullup resistor required. The pin goes low (active) when the FAULT condition is detected.
GND 19 1 Ground Digital and analog ground, connects to 0V
IOVDD 17 16 Input IO pin power supply
NC 4, 6, 8, 18 — — Must be left unconnected, pin floating
SCLK 14 13 Input Serial clock input of serial peripheral interface (SPI). Data can be transferred at rates up to 50MHz. Schmitt-trigger logic input
SDIN 15 14 Input Serial data input. Data are clocked into the register on the falling edge of the serial clock input. Schmitt-trigger logic input
SDO 13 12 Output Serial data output. Data are valid on the rising or falling edge of SCLK set by FSDO.
SYNC 16 15 Input SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, SDO is in Hi-Z.
VDD 20 2 Power Digital and analog power supply
VOUT 9 8 Output DAC voltage output pin
VREFGND 2 4 Input Reference ground, connects to 0V
VREFIO 1 3 Input/output Internal reference output or external reference input. Connect a 150nF capacitor to ground.
VSENSEN 11 10 Input Connect to 0V
VSENSEP 10 9 Input Sense output pin for the positive voltage output load connection