SLASEH4 November 2023 DAC61401 , DAC81401
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
To avoid any unintended I-R drop, connect VOUT and VSENSEP close to the load, and the voltage value for VSESNEP and VOUT must be same. Therefore, the gain stage output voltage is first buffered (U2) and then attenuated by a factor of 4 × with resistor divider R5 and R6.
VSENSEP has an input impedance of approximately 50 kῼ, and the resistor divider voltage cannot be connected directly, which causes erroneous voltage due to loading. This voltage output is first buffered (U3) and then connected to VSENSEP node of DAC81401 to close the internal feedback loop with VOUT.