SLASEH4 November   2023 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 5.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 5.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 5.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 5.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 5.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C; all typical values at TA = 25°C, AVDD = 4.5 V to 41.5 V, AVSS = –21.5 V to 0 V, VDD = 5.0 V, VREFIO = 2.5 V (external reference), IOVDD = 1.7 V, VSENSEN = 0 V, DAC output unloaded, CCOMP unconnected, digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution DAC81401 16 Bits
DAC61401 12 Bits
INL Relative accuracy(1) DAC81401,
all ranges except 0-V to 40-V range		 –1 ±0.4 1 LSB
DAC81401, 0-V to 40-V range –2 2 LSB
DAC61401 –1 1 LSB
DNL Differential nonlinearity –1 ±0.3 1 LSB
TUE Total unadjusted error(1) Unipolar ranges, AVSS = 0 V –0.09 0.09 %FSR
Unipolar ranges, AVSS = 0 V,
0°C ≤ TA ≤ +50°C		 –0.07 0.07
Bipolar ranges, –21.5 V ≤ AVSS < 0 V –0.085 0.085
OE Offset error(1) Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 –0.05 0.05 %FSR
OE-TC Offset error temperature coefficient Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 ±2 ppmFSR/°C
ZCE Zero-code (negative full scale) error Unipolar ranges, AVSS = 0 V 0.1 %FSR
Bipolar ranges, –21.5 V ≤ AVSS < 0 V 0.05
ZCE-TC Zero-code (negative full scale) error temperature coefficient Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 ±2 ppmFSR/°C
FSE Full-scale error(2) Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 –0.08 0.08 %FSR
FSE-TC Full-scale error temperature coefficient(2) ±3 ppmFSR/°C
GE Gain error(1) Unipolar ranges, AVSS = 0 V –0.075 0.075 %FSR
BPGE Gain error(1) Bipolar ranges, –21.5 V ≤ AVSS < 0 V –0.065 0.065 %FSR
GE-TC Gain error temperature coefficient ±2 ppmFSR/°C
BPZE Bipolar zero (midscale) error Bipolar ranges, –21.5 V ≤ AVSS < 0 V –0.03 0.03 %FSR
BPZE-TC Bipolar zero (midscale) error temperature coefficient Bipolar ranges, –21.5 V ≤ AVSS < 0 V ±2 ppmFSR/°C
Output voltage drift over time TA = 40°C, DAC code at full-scale, 1000 hours ±6 ppm FSR
OUTPUT CHARACTERISTICS
VOUT Output voltage  0 5 V
20% overrange of 0 V to 5 V 0 6
0 10
20% overrange of 0 V to 10 V 0 12
0 20
20% overrange of 0 V to 20 V 0 24
0 40
–5 5
20% overrange of –5 V to +5 V –6 6
–10 10
20% overrange of –10 V to +10 V –12 12
–20 20
Output voltage headroom (to AVDD) and footroom (to AVSS)(4) –10 mA ≤ load current ≤ 10 mA 1.25
5.5 V < AVDD ≤ 41.5 V, 
−15 mA ≤ load current ≤ +15 mA		 1.5 V
IOS Short-circuit current(3) Full-scale output shorted to AVSS 40 mA
Full-scale output shorted to AVDD,
5.5 V < AVDD ≤ 41.5 V,		 40
Zero-scale output shorted to AVDD,
4.5 V ≤ AVDD ≤ 5.5 V		 25
Load regulation DAC at midscale,
–15 mA ≤ load current ≤ +15 mA		 50 µV/mA
CL Capacitive load(4) RLOAD = open,
CCOMP pin left floating		 0 2 nF
RLOAD = open,
CCOMP pin = 470 pF ±10% to VOUT		 1 µF
IL Load current(4) 5.5 V < AVDD ≤ 41.5 V 15 mA
4.5 V < AVDD ≤ 5.5 V 10
VOUT dc output impedance DAC code at midscale, DAC unloaded 0.05 Ω
DAC code at full scale, DAC unloaded 0.05
DAC code at zero scale,
DAC unloaded, unipolar output		 35
DAC code at negative full scale,
DAC unloaded, bipolar output		 0.05
VSENSEP dc output impedance DAC code at midscale, 10-V span 55 kΩ
DAC disabled 45
DYNAMIC PERFORMANCE
Output voltage settling time 5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 7 µs
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 8 µs
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 12 µs
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 22 µs
5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMP = 470 pF to VOUT		 0.6 ms
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMP = 470 pF to VOUT		 0.6 ms
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMP = 470 pF to VOUT		 0.6 ms
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMP = 470 pF to VOUT		 1.2 ms
SR Slew rate 0-V to 5-V range (10% to 90% of full-scale range) 0.8 V/µs
All other output ranges except 40-V span (10% to 90% of full-scale range) 4
0-V to 5-V range, CL = 1 µF,
CCOMP = 470 pF to VOUT		 0.04
All other ranges, CL = 1 µF,
CCOMP = 470 pF to VOUT		 0.04
Power-on glitch magnitude AVSS and AVDD ramped symmetrically, ramp rate = 18 V/ms, output unloaded, internal reference 0.1 V
Output enable glitch magnitude AVSS and AVDD ramped, output unloaded, internal reference 0.35 V
VNOISEPP Output noise 0.1 Hz to 10 Hz,
DAC code at midscale,
10-V span, external reference = 2.5 V		 25 µVpp
0.1 Hz to 10 Hz,
DAC code at midscale,
10-V span, internal reference = 2.5 V		 30
VNOISE Output noise density 1 kHz, DAC code at midscale,
5-V span, output unloaded,
external reference		 115 nV/Hz
10 kHz, DAC code at midscale,
5-V span, output unloaded,
external reference		 105
THD Total harmonic distortion 1-kHz sine wave on VOUT, output unloaded, DAC update rate = 400 kHz 93 dB
PSRR-AC Power supply rejection ratio - ac VOUT = 0 V (midscale),
output unloaded, ±10-V output,
frequency = 60 Hz,
amplitude 200 mVPP,
superimposed on AVDD, VDD or AVSS		 75 dB
PSRR-DC Power supply rejection ratio - dc VOUT = 0 V (midscale), ±10-V output, VDD = 5 V, AVDD = 15 V ± 20%,
AVSS = –15 V, output unloaded		 5 µV/V
VOUT = 0 V (midscale), ±10-V output, VDD = 5 V, AVDD = 15 V,
AVSS = –15 V ± 20%, output unloaded		 10 µV/V
VOUT = 0 V (midscale), ±10-V output,
VDD = 5 V ± 5%, AVDD = 15 V,
AVSS = –15 V, output unloaded		 0.2 mV/V
VGL Code change glitch impulse 1-LSB change around midscale,
0-V to 5-V range, output unloaded		 1 nV-s
1-LSB change around midscale,
0-V to 10-V range, output unloaded		 2
1-LSB change around midscale,
–5-V to +5-V range, output unloaded		 2
1-LSB change around midscale,
–10-V to +10-V range, output unloaded		 4
Code change glitch amplitude 1-LSB change around midscale,
0-V to 5-V, 0-V to 10-V, –5-V to +5-V,
and –10-V to +10-V ranges,
output unloaded		 ±1.5 mV
Digital feedthrough DAC code at midscale, fSCLK = 1 MHz, output unloaded 0.3 nV-s
EXTERNAL REFERENCE INPUT
VREFIO Reference input voltage 2.49 2.5 2.51 V
IREF Reference input current 50 µA
ZIN Reference input impedance 50 kΩ
CREF Reference input capacitance 90 pF
INTERNAL REFERENCE
VREFO Reference output voltage  TA = 25°C 2.4975 2.5025 V
Reference output drift(3) 5 10 ppm/°C
RZO Reference output impedance 0.15 Ω
VNOISEPP Reference output noise 0.1 Hz to 10 Hz 12 µVpp
VNOISE Reference output noise density 10 kHz, VREFIO pin = 10 nF 240 nV/Hz
IL Reference load current Source 5 mA
Reference load regulation Source 120 µV/mA
Reference line regulation 100 µV/V
Reference output drift over time TA = 40°C, 1000 hours ±300 µV
Reference thermal hysteresis First cycle ±400 µV
Additional cycle ±35
DIGITAL INPUTS AND OUTPUTS
VIH SDIN, high-level input voltage 0.7 × IOVDD V
VIL SDIN, low-level input voltage 0.3 × IOVDD V
Input current ±2 µA
Input pin capacitance 2 pF
VOH SDO, high-level output voltage SDO load current = 0.2 mA IOVDD – 0.2 V
VOL SDO, low-level output voltage SDO load current = 0.2 mA 0.4 V
FAULT, low-level output voltage FAULT load current = 10 mA 0.4 V
Output pin capacitance 5 pF
POWER REQUIREMENTS(5)
IAVDD AVDD supply current(5) Normal mode, internal reference or external reference 1.6 mA
Power down mode 10 µA
IVDD VDD supply current(5) Digital interface static, internal reference or external reference 2.5 mA
IAVSS AVSS supply current(5) Normal mode, internal reference or external reference –1.6 mA
Power-down mode –10 µA
IIOVDD IOVDD supply current(5) SCLK toggling at 1 MHz 10 120 µA
(1) End point fit between codes. 16-bit: 512 to 65024 for AVDD ≥ 5.5 V, 512 to 63488 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO and AVDD; 12-bit: 32 to 4064 for AVDD ≥ 5.5 V, 32 to 3968 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO and AVDD.
(2) Full-scale code written to the DAC for AVDD ≥ 5.5 V. 16-bit: code 63488 written to the DAC for AVDD ≤ 5.5 V; 12-bit: code 3968 written to the DAC for AVDD ≤ 5.5 V.
(3) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation greater than the specified maximum junction temperature can impair device reliability.
(4) Specified by design and characterization, not production tested.
(5) Time to exit power down mode to normal operation. Measured from last rising edge of SYNC to 90% of DAC final value.