SLASEH3A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specifications at TA = 25°C, AVDD = 4.5 V to 41.5 V, AVSS = –21.5 V to 0 V, DVDD = 5.0 V, internal reference enabled, IOVDD = 1.7 V, VSENSENX = 0 V, CCOMPX floating, DAC outputs unloaded, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC81402 16 Bits
DAC61402 12
INL Relative accuracy(1) DAC81402. All ranges, except 0-V to 40-V and overranges –1 1 LSB
DAC81402. 0-V to 40-V range –2 2
DAC61402 –1 1
DNL Differential nonlinearity(1) –1 1 LSB
TUE Total unadjusted error(1) Unipolar ranges, AVSS = 0 V –0.07 0.07 %FSR
Unipolar ranges, AVSS = 0 V,
0℃ ≤ TA ≤ 50℃		 –0.05 0.05
Bipolar ranges, –21.5 V ≤ AVSS < 0 V –0.05 0.05
Offset error(1) Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 –0.05 0.05 %FSR
Offset error temperature coefficient Unipolar ranges, AVSS = 0 V
Bipolar ranges, –21.5 V ≤ AVSS < 0 V		 ±2 ppmFSR/°C
Zero-code (negative full scale) error All unipolar ranges, AVSS = 0 V 0.15 %FSR
All bipolar ranges,
–21.5 V ≤ AVSS < 0 V		 0.05
Zero-code (negative full scale) error temperature coefficient All unipolar ranges, AVSS = 0 V
All bipolar ranges,
–21.5 V ≤ AVSS < 0 V		 ±2 ppm of FSR/°C
Full-scale error(2) –0.06 0.06 %FSR
Full-scale error temperature coefficient(2) ±3 ppm of FSR/°C
Gain error(1) –0.06 0.06 %FSR
Gain error temperature coefficient ±2 ppm of FSR/°C
Bipolar-zero (midscale) error All bipolar ranges,
–21.5 V ≤ AVSS < 0 V		 –0.03 0.03 %FSR
Bipolar-zero (midscale) error temperature coefficient All bipolar ranges,
–21.5 V ≤ AVSS < 0 V		 ±2 ppm of FSR/°C
Output voltage drift over time TA = 40℃, DAC code = full scale, 1000 hours ±6 ppm FSR
OUTPUT CHARACTERISTICS
VOUT Output voltage 0 5 V
20% overrange 0 6
0 10
20% overrange 0 12
0 20
20% overrange 0 24
0 40
-5 5
20% overrange -6 6
–10 10
20% overrange –12 12
–20 20
Output voltage headroom and footroom to AVSS and AVDD
−10 mA ≤ load current ≤ 10 mA		 1.25 V
to AVSS and AVDD,
5.5 V < AVDD ≤ 41.5 V, 
−15 mA ≤ load current ≤ 15 mA		 1.5
Short circuit current(3) Full-scale output shorted to AVSS 40 mA
Zero-scale output shorted to AVDD,
5.5 V < AVDD ≤ 41.5 V, 		 40
Zero-scale output shorted to AVDD,
4.5 V ≤ AVDD ≤ 5.5 V		 25
Load regulation DAC at midscale,
−15 mA ≤ load current ≤ 15 mA		 50 µV/mA
CL Capacitive load(4) RLOAD = open, CCOMPX pin left floating 0 2 nF
RLOAD = open,
CCOMPX = 500 pF ± 10% to VOUTX 		1 µF
Load current(4) 5.5 V < AVDD ≤ 41.5 V 15 mA
4.5 V ≤ AVDD ≤ 5.5 V 10
VOUT dc output impedance DAC code at midscale, DAC unloaded 0.05 Ω
DAC code at full scale, DAC unloaded 0.05
DAC code at negative full scale,
DAC unloaded		 25
VSENSEP dc output impedance DAC code at midscale, 10-V span 55 kΩ
DAC disabled 45
VSENSEN dc output impedance DAC code at midscale, 10-V span 45 kΩ
DAC disabled 45
DYNAMIC PERFORMANCE
Output voltage settling time 5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 7 µs
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 8
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 12
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB 22
5-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMPX = 500 pF to VOUTX 		0.6 ms
10-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMPX = 500 pF to VOUTX 		0.6
20-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMPX = 500 pF to VOUTX 		0.6
40-V span, 1/4 to 3/4 scale and 3/4 to 1/4 scale, settling time to ±2 LSB,
CL = 1 µF, CCOMPX = 500 pF to VOUTX 		1.2
Slew rate 0-V to 5-V range (10% to 90% of full-scale range) 0.8 V/µs
All other output ranges except 40-V span (10% to 90% of full-scale range) 4
0-V to 5-V range, CL = 1 µF,
CCOMPX = 500 pF to VOUTX 		0.04
All other ranges, CL = 1 µF,
CCOMPX = 500 pF to VOUTX 		0.04
Power-on glitch magnitude AVSS and AVDD ramped symmetrically, ramp rate = 18 V/ms, output unloaded, internal reference 0.1 V
Output enable glitch magnitude AVSS and AVDD ramped, output unloaded, internal reference, gain = 1x 0.35 V
Output noise 0.1 Hz to 10 Hz, DAC code at midscale, 5-V span, external reference = 2.5 V, output unloaded 25 µVPP
0.1 Hz to 10 Hz, DAC code at midscale, 5-V span, internal reference = 2.5 V, output unloaded 30
Output noise density 1 kHz, DAC code at midscale, 5-V span, output unloaded, external reference 115 nV/√Hz
10 kHz, DAC code at midscale, 5-V span, output unloaded, external reference 105
THD Total harmonic distortion 1-kHz sine wave on VOUTX, output unloaded, DAC update rate = 400 kHz 88 dB
PSRR-AC Power supply ac rejection ratio VOUTX = 0 V (midscale), output unloaded, ±10-V output,
frequency = 60 Hz,
amplitude 200 mVPP,
superimposed on AVDD, DVDD or AVSS 		75 dB
PSRR-DC Power supply dc rejection ratio VOUTX = 0 V (midscale), ±10-V output, DVDD = 5 V, AVDD = 15 V ± 20%,
AVSS = –15 V, output unloaded		 5 µV/V
VOUTX = 0 V (midscale), ±10-V output, DVDD = 5 V, AVDD = 15 V,
AVSS = –15 V ± 20%, output unloaded		 10
VOUTX = 0 V (midscale), ±10-V output,
DVDD = 5 V ± 5%, AVDD = 15 V,
AVSS = –15 V, output unloaded		 0.2 mV/V
Code change glitch impulse 1-LSB change around midscale,
0-V to 5-V range, output unloaded		 1 nV-s
1-LSB change around midscale,
0-V to 10-V range, output unloaded		 2
1-LSB change around midscale,
–5-V to +5-V range, output unloaded		 2
1-LSB change around midscale,
–10-V to +10-V range, output unloaded		 4
Code change glitch amplitude 1-LSB change around midscale,
0-V to 5-V, 0-V to 10-V, –5-V to +5-V and –10-V to +10-V ranges, output unloaded		 ±10 mV
Channel-to-channel ac crosstalk 10-V span, full-scale swing on all other channel, measured channel at midscale, output unloaded 1 nV-s
Channel-to-channel dc crosstalk 10-V span, full-scale swing on all other channel, measured channel at midscale, output unloaded 1 LSB
Digital crosstalk 10-V span, full-scale swing on all other input buffer, measured channel at midscale, output unloaded 1 nV-s
Digital feedthrough DAC code at midscale, fSCLK = 1 MHz, output unloaded 1 nV-s
EXTERNAL REFERENCE INPUT
VREFIO Reference input voltage 2.49 2.5 2.51 V
Reference input current 50 µA
Reference input impedance 50 kΩ
Reference input capacitance 90 pF
INTERNAL REFERENCE
Reference output voltage TA = 25°C 2.4975 2.5025 V
Reference output drift 5 10 ppm/°C
Reference output impedance 0.15 Ω
Reference output noise 0.1 Hz to 10 Hz 12 µVPP
Reference output noise density 10 kHz, VREFIO = 10 nF 240 nV/√Hz
Reference load current 5 mA
Reference load regulation Source 120 µV/mA
Reference line regulation 100 µV/V
Reference output drift over time TA = 40°C, 1000 hours ±300 µV
Reference thermal hysteresis First cycle ±125 µV
Additional cycle ±25
DIGITAL INPUTS AND OUTPUTS
VIH Input high voltage 0.7 × IOVDD V
VIL Input low voltage 0.3 × IOVDD V
Input current ±2 µA
Input pin capacitance 2 pF
VOH SDO, high-level output voltage SDO load current = 0.2 mA IOVDD – 0.2 V
VOL SDO, low-level output voltage SDO load current = 0.2 mA 0.4 V
FAULT, low-level output voltage FAULT load current = 10 mA 0.4 V
Output pin capacitance 5 pF
POWER REQUIREMENTS
AIDD AVDD supply current(5) Normal mode, internal reference 8 mA
Normal mode, external reference 7
Power-down mode 10 µA
DIDD DVDD supply current(5) Digital interface static 8 mA
AISS AVSS supply current(5) Normal mode, internal reference –8 mA
Normal mode, external reference –7
Power-down mode –10 µA
IIOVDD IOVDD supply current(5) SCLK toggling at 1 MHz 100 µA
(1) End point fit between codes. 16-bit: 512 to 65024 for AVDD ≥ 5.5 V, 512 to 63488 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO and AVDD; 12-bit: 32 to 4064 for AVDD ≥ 5.5 V, 32 to 3968 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO and AVDD.
(2) Full-scale code written to the DAC for AVDD ≥ 5.5 V. 16-bit: code 63488 written to the DAC for AVDD ≤ 5.5 V; 12-bit: code 3968 written to the DAC for AVDD ≤ 5.5 V.
(3) Temporary overload condition protection. junction temperature can be exceeded during current limit. operation above the specified maximum junction temperature may impair device reliability.
(4) Specified by design and characterization, not production tested.
(5) AVDD = +15 V, AVSS = –15 V, DVDD = 5 V, SPI static, 10-V output span, all DAC at full scale, VOUTX unloaded.