SBASAK3A September   2022  – November 2022 DAC82001

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Power-On Reset (POR)
      3. 7.3.3 Hardware Reset
      4. 7.3.4 Software Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 SYNC Interrupt
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Arbitrary Waveform Generator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Analog Output Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +85°C and all typical values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V,
2.0 V ≤ VREF ≤ 5.5 V , AGND = 0 V, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 16 Bits
INL Integral nonlinearity –2 ±0.6 2 LSB
DNL Differential nonlinearity –1 ±0.5 1 LSB
TUE Total unadjusted error –0.06 0.04 0.06 %FSR
Zero code error –2.6 0.5 2.6 LSB
Zero code error temperature coefficient ±0.02 ppm/°C
Gain error –20 4 20 LSB
Gain error temperature coefficient ±0.1 ppm/°C
OUTPUT CHARACTERISTICS
VO Output voltage 0 VREF V
ZO Output impedance 6.25 kΩ
PSRR DC Power supply rejection ratio (dc) DAC at midscale; VDD = 5 V ±10%,
VREF = 2.5 V		 5 μV/V
DYNAMIC PERFORMANCE
ts Output voltage settling time To 1/2 LSB of FS, CL = 10 pF 1 µs
Output noise DAC at midcode, 0.1 Hz to 10 Hz 0.1 μVPP
Output noise density DAC at midcode, measured at 10 kHz 10 nV/√Hz
SFDR Spurious free dynamic range 1-kHz sinusoid at DAC output (unbuffered, full scale), DAC updated at 200 kSPS with 40-kHz low-pass filter, include up to 7th harmonics –96 dB
THD Total harmonic distortion 1-kHz sinusoid at DAC output (unbuffered, full scale), DAC updated at 200 kSPS with 40-kHz low-pass filter, include up to 7th harmonics –91 dB
PSRR AC Power supply rejection ratio (ac) DAC at midscale, VREF = 2.5 V,
VDD = 5 V ±200 mV at 10 kHz 		 –72 dB
Code change glitch impulse ±1 LSB around major carry  0.5 nV-s
Digital feedthrough 0.5 nV-s
Power on glitch magnitude CLOAD = 10 pF 0.8 V
VOLTAGE REFERENCE INPUT
Reference input voltage 2.0 VDD V
ZREF Reference input impedance 5 kΩ
CREF Reference input capacitance 75 pF
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input current –5 5 µA
Pin capacitance Per pin 10 pF
POWER
IDD Power-supply current VDD = 3 V 250 350 µA
VDD = 5 V 250 350
Power VDD = 3 V 750 1050 µW
VDD = 5 V 1250 1750