SBASAK3A September   2022  – November 2022 DAC82001

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Power-On Reset (POR)
      3. 7.3.3 Hardware Reset
      4. 7.3.4 Software Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 SYNC Interrupt
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Arbitrary Waveform Generator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Analog Output Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.15 V, 2.0 V ≤ VREF ≤ 5.5 V, and TA = –40°C to +85°C (unless otherwise noted)
MIN NOM MAX UNIT
fSCLK SCLK frequency 50 MHz
tSCLKHIGH SCLK high time 9 ns
tSCLKLOW SCLK low time 9 ns
tSDIS SDIN setup 5 ns
tSDIH SDIN hold 10 ns
tSYNCS SYNC falling edge to SCLK falling edge setup 13 ns
tSYNCH SCLK falling edge to SYNC rising  edge 10 ns
tSYNCHIGH SYNC high time 160 ns
tSYNCIGNORE SCLK falling edge to SYNC ignore 15 ns
tDACWAIT Sequential DAC update wait time 1 µs