9.1.1.1 DAC8x11 to 8051 Interface

Figure 81 shows a serial interface between the DAC8x11 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8x11, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data are to be transmitted to the DAC8x11, P3.3 is taken low. The 8051 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 remains low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC8x11 requires its data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this requirement into account, and mirror the data as needed.

Figure 81. DAC8x11 to 80C51/80l51 Interfaces

9.1.1.2 DAC8x11 to Microwire Interface

Figure 82 shows an interface between the DAC8x11 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and are clocked into the DAC8x11 on the rising edge of the SK signal.

Figure 82. DAC8x11 to Microwire Interface

9.1.1.3 DAC8x11 to 68HC11 Interface

Figure 83 shows a serial interface between the DAC8x11 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8x11, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051.

Figure 83. DAC8X11 to 68HC11 Interface

The 68HC11 should be configured so that its CPOL bit is a '0' and its CPHA bit is a '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is taken low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data are transmitted MSB first. In order to load data to the DAC8x11, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.

9.2.1.1 Design Requirements

The transmitter has only two external input terminals; a supply connection and a ground (or return) connection. The transmitter communicates back to the host, typically a PLC analog input module, by precisely controlling the magnitude of the return current. In order to conform to the 4-mA to 20-mA communication standards, the complete transmitter must consume less than 4 mA of current.

The complete design of this circuit is outlined in TIPD158, Low Cost Loop-Powered 4-20mA Transmitter EMC/EMI Tested Reference Design. The design is expected to be low-cost and deliver immunity to the IEC61000-4 suite of tests with minimum impact on the accuracy of the system. Reference design TIPD158 includes the design goals, simulated results, and measured performance.

9.2.1.2 Detailed Design Procedure

Amplifier U1 uses negative feedback to make sure that the potentials at the inverting (V–) and noninverting (V+) input terminals are equal. In this configuration, V– is directly tied to the local GND; therefore, the potential at the noninverting input terminal is driven to local ground. Thus, the voltage difference across R₂ is the DAC output voltage (VOUT), and the voltage difference across R₅ is the regulator voltage (VREG). These voltage differences cause currents to flow through R₂ and R₅, as illustrated in Figure 85.

Figure 85. Voltage to Current Conversion

The currents from R₂ and R₅ sum into i₁ (defined in Equation 1), and i₁ flows through R₃.

Equation 1.

Amplifier U2 drives the base of Q1, the NPN bipolar junction transistor (BJT), to allow current to flow through R₄ so that the voltage drops across R₃ and R₄ remain equal. This design keeps the inverting and noninverting terminals at the same potential. A small part of the current through R₄ is sourced by the quiescent current of all of the components used in the transmitter design (regulator, amplifier, and DAC). The voltage drops across R₃ and R₄ are equal; therefore, different-sized resistors cause different current flow through each resistor. Use these different-sized resistors to apply gain to the current flow through R₄ by controlling the ratio of resistor R₃ to R₄, as shown in Equation 2:

Equation 2.

The current gain in the circuit helps allow a majority of the output current to come directly from the loop through Q1 instead of from the voltage-to-current converter. This current gain, in addition to the low-power components, keeps the current consumption of the voltage-to-current converter low. Currents i₁ and i₂ sum to form output current i_out, as shown in Equation 3:

Equation 3.

The complete transfer function, arranged as a function of input code, is shown in Equation 4. The remaining sections divide this circuit into blocks for simplified discussion.

Equation 4.

Resistor R₆ is included to reduce the gain of transistor Q1, and therefore, reduce the closed-loop gain of the voltage-to-current converter for a stable design. Size resistors R₂, R₃, R₄, and R₅ based on the full-scale range of the DAC, regulator voltage, and the desired current output range of the design.

9.2.1.3 Application Curves

Figure 86 shows the measured transfer function of the circuit. Figure 87 shows the total unadjusted error (TUE) of the circuit, staying below 0.15 %FSR.

Figure 86. Output Current vs Code

Figure 87. Current Total Unadjusted Error vs Code