7.3.1 DAC Section

The architecture of the DAC8850 consists of a string DAC followed by an output buffer amplifier. Figure 46 shows the block diagram of the DAC architecture.

Figure 46. DAC8550 Architecture

The input coding to the DAC8550 is 2's complement, so the ideal output voltage is given by Equation 1.

Equation 1.

where

• D = decimal equivalent of the 2's complement code that is loaded to the DAC register

In Equation 1, D ranges from –32768 to 32767 where D = 0 is centered at V_REF / 2.

7.3.1.2 Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail output voltages with a range of 0 V to V_DD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.8 V/μs with a full-scale setting time of 8 μs with the output unloaded.

The inverting input of the output amplifier is brought out to the V_FB pin. This architecture allows for better accuracy in critical applications by tying the V_FB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications.

Figure 47. Resistor String

7.3.2 Power-On Reset

The DAC8550 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the output voltages are set to midscale; they remain that way until a valid write sequence is made to the DAC. The power-on reset is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.

7.4.1 Power-Down Modes

The DAC8550 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operation of the device.

When both bits are set to 0, the device works normally with a typical current consumption of 200 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The advantage with this configuration is that the output impedance of the device is known while in power-down mode. There are three different options. The output is connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated in Figure 48.

Figure 48. Output Stage During Power-Down

All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for V_DD = 5 V, and 5 μs for V_DD = 3 V. See the Typical Characteristics for more information.

7.5.1 Serial Interface

The DAC8550 has a 3-wire serial interface (SYNC, SCLK, and D_IN), which is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSP interfaces. See Figure 1 for an example of a typical write sequence.

The write sequence begins by bringing the SYNC line LOW. Data from the D_IN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the DAC8550 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is excuted (that is, a change in DAC register contents and/or a change in the mode of operation).

At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As mentioned above, it must be brought HIGH again just before the next write sequence.

7.5.2 Input Shift Register

The input shift register is 24 bits wide, as shown in Figure 49. The first six bits are unused bits. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). For a more complete description of the various modes see Power-Down Modes. The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK.

7.5.3 SYNC Interrupt

In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 50.

Figure 50. SYNC Interrupt Facility