SLASEB8C February 2016 – November 2016 DAC6551-Q1 , DAC8551-Q1
PRODUCTION DATA.
The DAC8551-Q1 and DAC6551-Q1 are small, low-power, voltage-output, 16- and 12-bit digital-to-analog converters (DACs) qualified for automotive applications. The DACx551-Q1 devices provide good linearity and minimize undesired code-to-code transient voltages. The devices use a versatile 3-wire serial interface that operates at clock rates to 30 MHz and is compatible with standard SPI, QSPI, Microwire, and digital signal-processor (DSP) interfaces.
The DACx551-Q1 devices require an external reference voltage to set the output range. The devices incorporate a power-on-reset circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the device takes place. The devices contain a power-down feature, accessed over the serial interface, that reduces the current consumption to 800 nA at 5 V.
The DACx551-Q1 devices power consumption is only 800 µW at 5 V, reducing to less than 4 μW in power-down mode. The DACx551-Q1 devices are available in a VSSOP-8 package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC8551-Q1 DAC6551-Q1 |
VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from B Revision (November 2016) to C Revision
Changes from A Revision (March 2016) to B Revision
Changes from * Revision (February 2016) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD to GND | –0.3 | 6 | V | |
Digital input voltage to GND | DIN, SCLK and SYNC | –0.3 | VDD + 0.3 | V |
VOUT to GND | –0.3 | VDD + 0.3 | V | |
VREF to GND | –0.3 | VDD + 0.3 | V | |
VFB to GND | –0.3 | VDD + 0.3 | V | |
Junction temperature range, TJ max | –65 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins | ±500 | |||
Corner pins (1, 4, 5, and 8) | ±750 |
THERMAL METRIC(1) | DAC8551-Q1 DAC6551-Q1 |
UNIT | |
---|---|---|---|
DGK (VSSOP) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 173.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 65.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 94.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 10.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 92.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
STATIC PERFORMANCE(1) | |||||||
Resolution | DAC8551-Q1 | 16 | Bits | ||||
DAC6551-Q1 | 12 | ||||||
Relative accuracy | DAC8551-Q1 | ±4 | ±16 | LSB | |||
DAC6551-Q1 | ±0.3 | ±1 | |||||
Differential nonlinearity | DAC8551-Q1 | ±0.35 | ±2 | LSB | |||
DAC6551-Q1 | ±0.02 | ±1 | |||||
Offset error | ±1 | ±15 | mV | ||||
Full-scale error | ±0.05 | ±0.5 | % of FSR | ||||
Gain error | ±0.02 | ±0.2 | % of FSR | ||||
Offset error drift | ±5 | μV/°C | |||||
Gain temperature coefficient | ±1 | ppm of FSR/°C | |||||
PSRR | Power-supply rejection ratio | RL = 2 kΩ, CL = 200 pF | 0.75 | mV/V | |||
OUTPUT CHARACTERISTICS(2) | |||||||
Output voltage range | 0 | VREF | V | ||||
Output voltage settling time | To ±0.003% FSR, 0200h to FD00h RL = 2 kΩ, 0 pF < CL < 200 pF |
8 | μs | ||||
Slew rate | 1.4 | V/μs | |||||
Capacitive load stability | RL = ∞ | 470 | pF | ||||
RL = 2 kΩ | 1000 | pF | |||||
Code change glitch impulse | 1 LSB change around major carry | 0.1 | nV-s | ||||
Digital feedthrough | 50 kΩ series resistance on digital lines | 0.1 | nV-s | ||||
DC output impedance | At mid-code input | 1 | Ω | ||||
Short-circuit current | VDD = 3 V to 5.5 V | 35 | mA | ||||
AC PERFORMANCE | |||||||
SNR | Signal-to-noise ratio | BW = 20 kHz, VDD = 5 V, VREF = 4.5 V, fOUT = 1 kHz First 19 harmonics removed for SNR calculation |
84 | dB | |||
THD | Total harmonic distortion | –80 | dB | ||||
SFDR | Spurious-free dynamic range | 84 | dB | ||||
SINAD | Signal to noise and distortion | 76 | dB | ||||
REFERENCE INPUT | |||||||
Reference current | VREF = VDD = 5.5 V | 50 | μA | ||||
VREF = VDD = 3.6 V | 25 | ||||||
Reference input range | 0 | VDD | V | ||||
Reference input impedance | 125 | kΩ | |||||
LOGIC INPUTS(2) | |||||||
Input current | ±1 | μA | |||||
VINL | Input low voltage | 0.3×VDD | V | ||||
VINH | Input high voltage | 0.7×VDD | V | ||||
Pin capacitance | 3 | pF | |||||
POWER REQUIREMENTS | |||||||
VDD | Supply voltage | 3 | 5.5 | V | |||
IDD | Supply current | Normal mode, midscale code, no load, does not include reference current. VIH = VDD and VIL = GND, VDD = 3.6 V to 5.5 V |
160 | 250 | μA | ||
Normal mode, midscale code, no load, does not include reference current. VIH = VDD and VIL = GND, VDD = 3 V to 3.6 V |
110 | 240 | |||||
All power-down modes, VIH = VDD and VIL = GND, VDD = 3.6 V to 5.5 V |
0.8 | 3 | |||||
All power-down modes, VIH = VDD and VIL = GND, VDD = 3 V to 3.6 V |
0.5 | 3 | |||||
POWER EFFICIENCY | |||||||
IOUT / IDD | ILOAD = 2 mA, VDD = 5 V | 89% | |||||
TEMPERATURE RANGE | |||||||
TA | Ambient temperature | –40 | 125 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Power-up time | Coming out of power-down mode, VDD = 5 V | 2.5 | µs | |||
Coming out of power-down mode, VDD = 3.3 V | 5 |
The DAC8551-Q1 and DAC6551-Q1 are small, low-power, voltage-output, 16- and 12-bit digital-to-analog converters (DACs) qualified for automotive applications. The DACx551-Q1 devices provide good linearity and minimize undesired code-to-code transient voltages. The devices use a versatile 3-wire serial interface that operates at clock rates to 30 MHz and is compatible with standard SPI, QSPI, Microwire, and digital signal processor (DSP) interfaces.
The DACx551-Q1 devices require an external reference voltage to set the output range. The devices incorporate a power-on-reset circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the device takes place. The devices contain a power-down feature, accessed over the serial interface, that reduces the current consumption to 800 nA at 5 V.
The DACx551-Q1 devices power consumption is only 800 µW at 5 V, reducing to less than 4 μW in power-down mode. The DACx551-Q1 devices are available in a VSSOP-8 package.
The DACx551-Q1 architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture.
The input coding to the DACx551-Q1 is straight binary, so the ideal output voltage is given by:
where:
The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.4 V/μs with a full-scale setting time of 8 μs with the output unloaded.
The inverting input of the output amplifier is brought out to the VFB pin. This configuration allows for better accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications.
The DACx551-Q1 contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DAC registers are filled with zeros and the output voltages are 0 V; they remain that way until a valid write sequence is made to the DAC. The power-on reset is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
The DACx551-Q1 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operation of the device.
PD1 (DB17) | PD0 (DB16) | OPERATING MODE |
---|---|---|
0 | 0 | Normal operation |
— | — | Power-down modes |
0 | 1 | Output typically 1 kΩ to GND |
1 | 0 | Output typically 100 kΩ to GND |
1 | 1 | High-Z |
When both bits are set to 0, the device works normally with its typical current consumption of 160 μA at 5 V. However, for the three power-down modes, the supply current falls to 800 nA at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This configuration has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options. The output is connected internally to GND through a 1‑kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated in Figure 29.
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power down. The time to exit power-down is typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V. See the Typical Characteristics for more information.
The DAC8551-Q1 and DAC6551-Q1 devices have a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation Timing Diagram section for an example of a typical write sequence.
The input shift register is 24 bits wide, as shown in Figure 30 and Figure 31. The first six bits are don't care bits. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). A more complete description of the various modes is located in the Power-Down Modes section. The next 16 bits are the left aligned data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK.
DB23 | DB0 | ||||||||||||||||||||||
X | X | X | X | X | X | PD1 | PD0 | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
DB23 | DB0 | ||||||||||||||||||||||
X | X | X | X | X | X | PD1 | PD0 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | 0 | 0 | 0 | 0 |
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the devices compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change in the mode of operation).
At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought high again just before the next write sequence.
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 32.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DAC8551-Q1 and DAC6551-Q1 devices are AEC-Q100 qualified, low-power, ultralow-glitch, 16-bit and 12-bit DACs, respectively. The wide temperature range, low-power consumption and very low glitch of the devices make them a great choice for automotive applications such as radar and sensor conditioning.
This design is commonly referred to as a loop-powered, or 2-wire, 4 mA to 20 mA transmitter. The transmitter has only two external input terminals: a supply connection and an output, or return, connection. The transmitter communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its return current. In order to conform to the 4 mA to 20 mA communication standard, the complete transmitter must consume less than 4 mA of current. The DAC8551-Q1 device enables the accurate control of the loop current from 4 mA to 20 mA in 16-bit steps.
Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides simplicity and improved performance due to the matched internal resistors. The output current can be modified if necessary by looking using Equation 2.
For more details of this application, see 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7). It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.
The DAC8551-Q1 device has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 36. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
The output voltage for any input code can be calculated as follows:
where D represents the input code in decimal (0–65,535)
with VREF = 5V, R1 = R2 = 10 kΩ.
Using this example, an output voltage range of ±5 V with 0000h corresponding to a –5 V output and FFFFh corresponding to a 5 V output can be achieved. Similarly, using VREF = 2.5 V, a ±2.5 V output voltage range can be achieved.
Due to the extremely low supply current required by the DACx551-Q1, an alternative option is to use a precision reference such as the REF02 device to supply the required voltage to the device, as illustrated in Figure 37.
This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 device outputs a steady supply voltage for the device. If the REF02 device is used, the current it must supply to the device is 200 μA. This configuration is with no load on the output of the DAC. When a DAC output is loaded, the REF02 also must supply the current to the load.
The total current required (with a 5 kΩ load on the DAC output) is:
The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2 mA current drawn from it. This value corresponds to a 3.9 LSB error.
See Figure 38 for a serial interface between the DACx551-Q1 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DACx551-Q1, whereas RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data are to be transmitted to the DACx551-Q1, P3.3 is taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DACx551-Q1 requires data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this into account, and mirror the data as needed.
Figure 39 shows an interface between the DACx551-Q1 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and is clocked into the DACx551-Q1 on the rising edge of the SK signal.
Figure 40 shows a serial interface between the DACx551-Q1 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the DACx551-Q1, whereas the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DACx551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write operation are performed to the DAC. PC7 is taken high at the end of this procedure.
The DACx551-Q1 can operate within the specified supply voltage range of 3 V to 5.5 V. The power applied to VDD should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. In order to further minimize noise from the power supply, a strong recommendation is to include a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical Characteristics table. The power supply must meet the aforementioned current requirements.