SLASEB8C February   2016  – November 2016 DAC6551-Q1 , DAC8551-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Section
        1. 7.3.1.1 Resistor String
        2. 7.3.1.2 Output Amplifier
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 SYNC Interrupt
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Operation Using the DAC8551-Q1 Device
      3. 8.2.3 Using the REF02 As a Power Supply for the DACx551-Q1
    3. 8.3 System Examples
      1. 8.3.1 Interface From the DACx551-Q1 to 8051
      2. 8.3.2 Interface From the DACx551-Q1 to Microwire
      3. 8.3.3 Interface From the DACx551-Q1 to 68HC11
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
DIN 7 I Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-trigger logic input.
GND 8 GND Ground reference point for all circuitry on the device
SCLK 6 I Serial clock input. Data can be transferred at rates up to 30 MHz. Schmitt-trigger logic input.
SYNC 5 I Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC going low enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device). Schmitt-trigger logic input.
VDD 1 PWR Power supply input, 3 V to 5.5 V
VFB 3 I Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
VOUT 4 O Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
VREF 2 I Reference voltage input