SLAS464C December   2006  – January 2018 DAC8560

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Typical Characteristics: Internal Reference
    8. 6.8  Typical Characteristics: DAC at VDD = 5 V
    9. 6.9  Typical Characteristics: DAC at VDD = 3.6 V
    10. 6.10 Typical Characteristics: DAC at VDD = 2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC)
      2. 7.3.2 Resistor String
      3. 7.3.3 Output Amplifier
      4. 7.3.4 DAC Noise Performance
      5. 7.3.5 Internal Reference
        1. 7.3.5.1 Enable/Disable Internal Reference
        2. 7.3.5.2 Internal Reference Load
          1. 7.3.5.2.1 Supply Voltage
          2. 7.3.5.2.2 Temperature Drift
          3. 7.3.5.2.3 Noise Performance
          4. 7.3.5.2.4 Load Regulation
          5. 7.3.5.2.5 Long-Term Stability
          6. 7.3.5.2.6 Thermal Hysteresis
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Input Shift Register
      3. 7.5.3 SYNC Interrupt
      4. 7.5.4 Power-On Reset
    6. 7.6 Register Maps
      1. 7.6.1 Write Sequence for Disabling the DAC8560 Internal Reference
        1. Table 1. Write Sequence for Disabling the DAC8560 Internal Reference
      2. 7.6.2 Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
        1. Table 2. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
      3. 7.6.3 Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
        1. Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
      4. 7.6.4 DAC8560 Data Input Register Format
        1. Table 4. DAC8560 Data Input Register Format
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure or Bipolar Operation > ±VREF
        1. 8.2.2.1 Bipolar Operation Greater Than ±VREF
          1. 8.2.2.1.1 Passive Component Selection
          2. 8.2.2.1.2 Amplifier Selection
        2. 8.2.2.2 Microprocessor Interfacing
          1. 8.2.2.2.1 DAC8560 to 8051 Interface
          2. 8.2.2.2.2 DAC8560 to Microwire Interface
          3. 8.2.2.2.3 DAC8560 to 68HC11 Interface
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VDD = 2.7 V to 5.5 V, –40°C to +105°C range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
Relative accuracy Measured by line passing through codes 485 and 64714 DAC8560A, DAC8560C ±4 ±12 LSB
DAC8560B, DAC8560D ±4 ±8 LSB
Differential nonlinearity 16-bit Monotonic ±0.5 ±1 LSB
Zero-code error Measured by line passing through codes 485 and 64714. ±5 ±12 mV
Full-scale error ±0.2 ±0.5 % of FSR
Gain error ±0.05 ±0.2 % of FSR
Zero-code error drift ±4 μV/°C
Gain temperature coefficient VDD = 5 V ±1 ppm of
FSR/°C
VDD = 2.7 V ±3
PSRR Power supply rejection ratio Output unloaded 1 mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range 0 VREF V
Output voltage settling time To ±0.003% FSR, 0200h to FD00h, RL = 2 kΩ,
0 pF < CL < 200 pF		 8 10 μs
RL = 2 kΩ, CL = 500 pF 12
Slew rate 1.8 V/μs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000
Code change glitch impulse 1 LSB change around major carry 0.15 nV-s
Digital feedthrough SCLK toggling, SYNC high 0.15 nV-s
DC output impedance At mid-code input 1 Ω
Short-circuit current VDD = 5 V 50 mA
VDD = 3 V 20
Power-up time Coming out of power-down mode VDD = 5 V 2.5 μs
Coming out of power-down mode VDD = 3 V 5
AC PERFORMANCE(2)
SNR TA = 25°C, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation		 88 dB
THD –77 dB
SFDR 79 dB
SINAD 77 dB
DAC output noise density TA = 25°C, at mid-code input, fOUT = 1 kHz 170 nV/√Hz
DAC output noise TA = 25°C, at mid-code input, 0.1 Hz to 10 Hz 50 μVPP
REFERENCE OUTPUT
Output voltage TA = 25°C 2.4975 2.5 2.5025 V
Initial accuracy TA = 25°C –0.1% ±0.004% 0.1%
Output voltage temperature drift DAC8560A, DAC8560B(3) 5 25 ppm/°C
DAC8560C, DAC8560D(4) 2 5
Output voltage noise f = 0.1 Hz to 10 Hz 16 μVPP
Output voltage noise density
(high-frequency noise)		 TA = 25°C, f = 1 MHz, CL = 0 μF 125 nV/√Hz
TA = 25°C, f = 1 MHz, CL = 1 μF 20
TA = 25°C, f = 1 MHz, CL = 4 μF 2
Load regulation, sourcing(5) TA = 25°C 30 μV/mA
Load regulation, sinking(5) TA = 25°C 15 μV/mA
Output current load capability(2) ±20 mA
Line regulation TA = 25°C 10 μV/V
Long-term stability/drift (aging)(5) TA = 25°C, time = 0 to 1900 hours 50 ppm
Thermal hysteresis(5) First cycle 100 ppm
Additional cycles 25
REFERENCE
Internal reference current consumption VDD = 5.5 V 360 μA
VDD = 3.6 V 348
External reference current External VREF = 2.5 V, if internal reference is disabled 20 μA
Reference input range 0 VDD V
Reference input impedance 125 kΩ
LOGIC INPUTS (2)
Input current ±1 μA
VINL Logic input LOW voltage VDD = 5 V 0.8 V
VDD = 3 V 0.6
VINH Logic input HIGH voltage VDD = 5 V 2.4 V
VDD = 3 V 2.1
Pin capacitance 3 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD(6) Normal mode
VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND 0.53 0.85 mA
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND 0.51 0.84
All power-down modes VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND 1.2 2.5 μA
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND 0.7 2.2
Power dissipation(6) Normal mode VDD = 3.6 V to 5.5 V 2.6 4.7 mW
VDD = 2.7 V to 3.6 V 1.5 3
All power-down modes VDD = 3.6 V to 5.5 V 6 14 μW
VDD = 2.7 V to 3.6 V 2 8
TEMPERATURE RANGE
Specified performance –40 105 °C
(1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
(2) Ensured by design and characterization, not production tested.
(3) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
(4) Reference is trimmed and tested at two temperatures (25°C and 105°C), and is characterized from –40°C to +120°C.
(5) Explained in more detail in Application and Implementation.
(6) Input code = 32768, reference current included, no load.