SBAS430F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements
    4. 7.4 Typical Characteristics: Internal Reference
    5. 7.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 7.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 7.7 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Digital-to-Analog Converter (DAC)
      2. 8.2.2  Resistor String
      3. 8.2.3  Output Amplifier
      4. 8.2.4  Internal Reference
      5. 8.2.5  Serial Interface
      6. 8.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 8.2.7  SYNC Interrupt
      8. 8.2.8  Power-on Reset to Zero Scale or Midscale
      9. 8.2.9  Clear Code Register and CLR Pin
      10. 8.2.10 Software Reset Function
      11. 8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 8.3 Device Functional Modes
      1. 8.3.1 Enable/Disable Internal Reference
        1. 8.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 8.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 8.3.2 LDAC Functionality
      3. 8.3.3 Power-Down Modes
        1. 8.3.3.1 DAC Power-Down Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications - Microprocessor Interfacing
      1. 9.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Internal Reference
            1. 9.2.1.1.1.1 Supply Voltage
            2. 9.2.1.1.1.2 Temperature Drift
            3. 9.2.1.1.1.3 Noise Performance
            4. 9.2.1.1.1.4 Load Regulation
            5. 9.2.1.1.1.5 Long-Term Stability
            6. 9.2.1.1.1.6 Thermal Hysteresis
          2. 9.2.1.1.2 DAC Noise Performance
          3. 9.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 9.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 9.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Static Performance
          1. 11.1.1.1.1  Resolution
          2. 11.1.1.1.2  Least Significant Bit (LSB)
          3. 11.1.1.1.3  Most Significant Bit (MSB)
          4. 11.1.1.1.4  Relative Accuracy or Integral Nonlinearity (INL)
          5. 11.1.1.1.5  Differential Nonlinearity (DNL)
          6. 11.1.1.1.6  Full-Scale Error
          7. 11.1.1.1.7  Offset Error
          8. 11.1.1.1.8  Zero-Code Error
          9. 11.1.1.1.9  Gain Error
          10. 11.1.1.1.10 Full-Scale Error Drift
          11. 11.1.1.1.11 Offset Error Drift
          12. 11.1.1.1.12 Zero-Code Error Drift
          13. 11.1.1.1.13 Gain Temperature Coefficient
          14. 11.1.1.1.14 Power-Supply Rejection Ratio (PSRR)
          15. 11.1.1.1.15 Monotonicity
        2. 11.1.1.2 Dynamic Performance
          1. 11.1.1.2.1  Slew Rate
          2. 11.1.1.2.2  Output Voltage Settling Time
          3. 11.1.1.2.3  Code Change/Digital-to-Analog Glitch Energy
          4. 11.1.1.2.4  Digital Feedthrough
          5. 11.1.1.2.5  Channel-to-Channel DC Crosstalk
          6. 11.1.1.2.6  Channel-to-Channel AC Crosstalk
          7. 11.1.1.2.7  Signal-to-Noise Ratio (SNR)
          8. 11.1.1.2.8  Total Harmonic Distortion (THD)
          9. 11.1.1.2.9  Spurious-Free Dynamic Range (SFDR)
          10. 11.1.1.2.10 Signal-to-Noise plus Distortion (SINAD)
          11. 11.1.1.2.11 DAC Output Noise Density
          12. 11.1.1.2.12 DAC Output Noise
          13. 11.1.1.2.13 Full-Scale Range (FSR)
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Timing Requirements(1)(2)

At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 SCLK falling edge to SYNC falling edge (for successful write operation) AVDD = 2.7V to 5.5V 10 ns
t2(3) SCLK cycle time AVDD = 2.7V to 5.5V 20 ns
t3 SYNC rising edge to 31st SCLK falling edge (for successful SYNC interrupt) AVDD = 2.7V to 5.5V 13 ns
t4 Minimum SYNC HIGH time AVDD = 2.7V to 5.5V 80 ns
t5 SYNC to SCLK falling edge setup time AVDD = 2.7V to 5.5V 13 ns
t6 SCLK LOW time AVDD = 2.7V to 5.5V 8 ns
t7 SCLK HIGH time AVDD = 2.7V to 5.5V 8 ns
t8 SCLK falling edge to SYNC rising edge AVDD = 2.7V to 5.5V 10 ns
t9 Data setup time AVDD = 2.7V to 5.5V 6 ns
t10 Data hold time AVDD = 2.7V to 5.5V 4 ns
t11 SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode AVDD = 2.7V to 5.5V 40 ns
t12 LDAC pulse width LOW time AVDD = 2.7V to 5.5V 80 ns
t13 LDAC falling edge to SCLK falling edge for synchronous LDAC update mode AVDD = 2.7V to 5.5V 4 × t1 ns
t14 32nd SCLK falling edge to LDAC rising edge AVDD = 2.7V to 5.5V 40 ns
t15 CLR pulse width LOW time AVDD = 2.7V to 5.5V 80 ns
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AVDD = 2.7V to 5.5V.
DAC7568 DAC8168 DAC8568 tim_ser_write_op_bas430.gif
1. Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
2. Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
Figure 1. Serial Write Operation