SBAS940 December 2018 DAC8742H
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
POWER REQUIREMENTS | |||||
IOVDD | 1.71 | 5.5 | V | ||
AVDD | 2.7 | 5.5 | V | ||
AVDD and IOVDD Supply Current (HART Mode) | |||||
Demodulator active | External Clock, -40°C to 85°C | 110 | 150 | µA | |
External Clock, -55°C to 125°C | 220 | µA | |||
External Clock, -40°C to 85°C, External Reference | 100 | 140 | µA | ||
External Clock, -55°C to 125°C, External Reference | 210 | µA | |||
Modulator active | External Clock, -40°C to 85°C | 160 | 180 | µA | |
External Clock, -55°C to 125°C | 250 | µA | |||
External Clock, -40°C to 85°C, External Reference | 150 | 170 | µA | ||
External Clock, -55°C to 125°C, External Reference | 240 | µA | |||
Crystal Oscillator | External Crystal, 16pF at XTAL1 and XTAL2 | 40 | 65 | µA | |
External Crystal, 36pF at XTAL1 and XTAL2 | 40 | 65 | µA | ||
Internal Oscillator | External Reference | 105 | 180 | µA | |
SPI Interface | Additional quiescent current required when interfacing via SPI | 5 | µA | ||
AVDD and IOVDD Supply Current (FF/PA Mode) | |||||
Decoder active | External Clock, -40°C to 85°C | 160 | 220 | µA | |
External Clock, -55°C to 125°C | 330 | µA | |||
External Clock, -40°C to 85°C, External Reference | 175 | 200 | µA | ||
External Clock, -55°C to 125°C, External Reference | 320 | µA | |||
Encoder active | External Clock, -40°C to 85°C | 175 | 250 | µA | |
External Clock, -55°C to 125°C | 360 | µA | |||
External Clock, -40°C to 85°C, External Reference | 165 | 235 | µA | ||
External Clock, -55°C to 125°C, External Reference | 350 | µA | |||
Crystal Oscillator | External Crystal, 16pF at XTAL1 and XTAL2 | 40 | 65 | µA | |
External Crystal, 36pF at XTAL1 and XTAL2 | 40 | 65 | µA | ||
SPI Interface | Additional quiescent current required when interfacing via SPI | 5 | µA | ||
AVDD and IOVDD Supply Current (All Modes) | |||||
Power-Down Mode | Internal reference disabled, -40°C to 85°C, no active clock input | 30 | 60 | µA | |
Internal reference disabled, -55°C to 125°C, no active clock input | 182 | µA | |||
CLOCK REQUIREMENTS | |||||
EXTERNAL CLOCK (HART MODE) | |||||
External Clock Source Frequency | 3.6864 MHz Clock | 3.6469 | 3.6864 | 3.7232 | MHz |
1.2288 MHz Clock | 1.2165 | 1.2288 | 1.2411 | MHz | |
EXTERNAL CLOCK (FF/PA MODE) | |||||
External Clock Source Frequency | 4 MHz Clock | 3.96 | 4 | 4.04 | MHz |
INTERNAL OSCILLATOR | |||||
Frequency | -40°C to 125°C | 1.2165 | 1.2288 | 1.2411 | MHz |
VOLTAGE REFERENCE | |||||
INTERNAL REFERENCE VOLTAGE | |||||
Internal Reference Voltage | 1.47 | 1.5 | 1.53 | V | |
Load Regulation | 1.3 | V/mA | |||
Capacitive Load | Guaranteed by design | 1 | µF | ||
OPTIONAL EXTERNAL REFERENCE VOLTAGE | |||||
External Reference Input Voltage | 2.375 | 2.5 | 2.625 | V | |
External Reference Input Current | Demodulator | 4.5 | µA | ||
Modulator | 4.5 | µA | |||
Internal Oscillator | 4.5 | µA | |||
Power-Down | 4.5 | µA | |||
HART MODEM | |||||
MOD_IN INPUT (HART MODE) | |||||
Input Voltage Range | External Reference Source, guaranteed by design. Signal applied at the input to the DC blocking capacitor. | 0 | 1.5 | Vp-p | |
Internal Reference Source, guaranteed by design. Signal applied at the input to the DC blocking capacitor. | 0 | 1.5 | Vp-p | ||
Receiver Sensitivity | Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. | 80 | 100 | 120 | mVp-p |
MOD_OUT OUTPUT (HART MODE) | |||||
Output Voltage | AC-coupled (2.2µF), measured at MOD_OUT pin with 160Ω load | 450 | 460 | 480 | mVp-p |
Mark Frequency | Internal Oscillator | 1200 | Hz | ||
Space Frequency | Internal Oscillator | 2200 | Hz | ||
Frequency Error | Internal Oscillator, -40°C to 125°C | -1 | 1 | % | |
Phase Continuity Error | Guaranteed by design | 0 | Degrees | ||
Minimum Resistive Load | 160Ω, AC coupled with 2.2µF, guaranteed by design | 160 | Ω | ||
Transmit Impedance | RTS low, measured at the MOD_OUT pin, 1mA measurement current | 13 | Ω | ||
RTS high, measured at the MOD_OUT pin, ±200nA measurement current | 250 | kΩ | |||
FF / PA MODEM | |||||
MOD_IN INPUT (FF/PA MODE) | |||||
Input Voltage Range | External Reference Source, specified by design. Signal applied at the input to the DC blocking capacitor. | 0 | 1 | Vp-p | |
Internal Reference enabled, specified by design. Signal applied at the input to the DC blocking capacitor. | 0 | 1 | Vp-p | ||
Receiver Jitter Tolerance | Edge-to-edge measurement of Manchester Encoded waveforms | -3.2 | 3.2 | µs | |
Receiver Sensitivity | Threshold for successful carrier detection and decoding, assuming ideal Manchester Encoded input trapezoidal signals with 6µs rise time, valid preamble byte(s) and start delimiter byte, using internal filter. | 75 | mVp-p | ||
MOD_OUT OUTPUT (FF/PA MODE) | |||||
Output Voltage | 800 | mVp-p | |||
Maximum Amplitude Difference | Maximum difference in positive and negative amplitude signals | -50 | 50 | mV | |
Transmit Bit Rate | 31.1875 | 31.25 | 31.3125 | kbit/s | |
Transmit Jitter | Measured with respect to ideal crossing of high time and low time | -0.8 | 0.8 | µs | |
Output Signal Distortion | Measured peak to trough distortion for positive and negative amplitude voltage outputs | -10 | 10 | % | |
Rise and Fall Time | 10% to 90% of peak to peak signal | 8 | µs | ||
Slew Rate | 10% to 90% of peak to peak signal | 0.2 | V/µs | ||
DIGITAL REQUIREMENTS | |||||
DIGITAL INPUTS | |||||
VIH, Input High Voltage | 0.7 x IOVDD | V | |||
VIL, Input Low Voltage | 0.3 x IOVDD | V | |||
CLK_CFG0, Input High Voltage | Guaranteed by design | 0.8 x IOVDD | V | ||
CLK_CFG0, Input Mid-Scale Voltage | Guaranteed by design | 0.4 x IOVDD | 0.55 x IOVDD | V | |
CLK_CFG0, Input Low Voltage | Guaranteed by design | 0.15 x IOVDD | |||
Input Current | -1 | 1 | µA | ||
Input Capcitance | 5 | pF | |||
DIGITAL OUTPUTS | |||||
VOH, Output High Voltage | 200µA source/sink | IOVDD - 0.5 | V | ||
VOL, Output Low Voltage | 200µA source/sink | 0.4 | V |