SBAS538D December   2013  – December 2021 DAC7750 , DAC8750

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Current Output Stage
      3. 8.3.3  Internal Reference
      4. 8.3.4  Digital Power Supply
      5. 8.3.5  DAC Clear
      6. 8.3.6  Power-On Reset
      7. 8.3.7  Alarm Detection
      8. 8.3.8  Watchdog Timer
      9. 8.3.9  Frame Error Checking
      10. 8.3.10 User Calibration
      11. 8.3.11 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Current-Output Ranges
      2. 8.4.2 Current-Setting Resistor
      3. 8.4.3 BOOST Configuration for IOUT
      4. 8.4.4 Filtering The Current Output
      5. 8.4.5 Output Current Monitoring
      6. 8.4.6 HART Interface
        1. 8.4.6.1 Implementing HART in 4-mA to 20-mA Mode
        2. 8.4.6.2 Implementing HART in All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx750 Register Descriptions
        1. 8.6.1.1 Control Register
        2. 8.6.1.2 Configuration Register
        3. 8.6.1.3 DAC Registers
        4. 8.6.1.4 Reset Register
        5. 8.6.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 HART Implementation
        1. 9.1.1.1 Using the CAP2 Pin
        2. 9.1.1.2 Using the ISET-R Pin
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision C (January 2018) to Revision D (December 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed Loop compliance voltage to Reference input voltage, and Reference input voltage to External reference current in Recommended Operating Conditions Go
  • Changed Digital input low voltage test condition upper limit from 2.6 V to 3.6 V in Recommended Operating Conditions Go
  • Deleted Timing Requirements: Daisy-Chain Mode section and Daisy-Chain Mode Timing figureGo
  • Deleted Power-Supply Sequence section; content moved to Power Supply Recommendations sectionGo
  • Deleted daisy-chain operation content from Watchdog Timer sectionGo
  • Deleted The DACx750 Shares the SPI Bus With Other Devices subsection from Watchdog Timer sectionGo
  • Deleted daisy-chain operation from Frame Error Checking sectionGo
  • Added CRC fault reset command of 0x96 to Frame Error Checking sectionGo
  • Deleted The DACx750 Shares the SPI Bus With Other Devices subsectionGo
  • Changed duplicated 010 step-size from 0.125 to 0.25 in Table 8-3, Slew Rate Step-Size Options Go
  • Added CRC fault reset command to Table 8-8, Write Address Functions Go
  • Deleted Daisy-Chain Operation sectionGo
  • Added Multiple Devices on the Bus sectionGo
  • Changed Table 8-11 to delete daisy-chain operation and add CRC fault resetGo
  • Changed DCEN to Reserved for DB3 in Control Register tableGo
  • Deleted text stating CAP2 pin is only available for the 40-pin VQFN packageGo
  • Added series resistance for supply and corrected HART-IN capacitance for Figure 9-3Go
  • Added content from deleted Power-Supply Sequence section to Power Supply Recommendations sectionGo
  • Added fast supply ramp and series resistance content to Power-Supply Recommendations Go
  • Added power supply series resistance to Figure 11-1, Layout Example Go

Changes from Revision B (June 2016) to Revision C (January 2018)

  • Added last paragraph to User Calibration sectionGo
  • Added last paragraph to Programmable Slew Rate sectionGo