SBAS538D December   2013  – December 2021 DAC7750 , DAC8750

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Current Output Stage
      3. 8.3.3  Internal Reference
      4. 8.3.4  Digital Power Supply
      5. 8.3.5  DAC Clear
      6. 8.3.6  Power-On Reset
      7. 8.3.7  Alarm Detection
      8. 8.3.8  Watchdog Timer
      9. 8.3.9  Frame Error Checking
      10. 8.3.10 User Calibration
      11. 8.3.11 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Current-Output Ranges
      2. 8.4.2 Current-Setting Resistor
      3. 8.4.3 BOOST Configuration for IOUT
      4. 8.4.4 Filtering The Current Output
      5. 8.4.5 Output Current Monitoring
      6. 8.4.6 HART Interface
        1. 8.4.6.1 Implementing HART in 4-mA to 20-mA Mode
        2. 8.4.6.2 Implementing HART in All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx750 Register Descriptions
        1. 8.6.1.1 Control Register
        2. 8.6.1.2 Configuration Register
        3. 8.6.1.3 DAC Registers
        4. 8.6.1.4 Reset Register
        5. 8.6.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 HART Implementation
        1. 9.1.1.1 Using the CAP2 Pin
        2. 9.1.1.2 Using the ISET-R Pin
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at AVDD = 10 V to 36 V, GND = 0 V, REFIN = 5 V external, DVDD = 2.7 V to 5.5 V, and all specifications are from –40°C to +125°C (unless otherwise noted); for IOUT, RL = 300 Ω; typical specifications are at 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CURRENT OUTPUT
Current outputRANGE bits = 111024mA
RANGE bits = 110020
RANGE bits = 101420
ResolutionDAC875016Bits
DAC775012
CURRENT OUTPUT ACCURACY (0 mA TO 20 mA AND 0 mA TO 24 mA)(1)
Total unadjusted error, TUETA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.16%0.16%
TA = 25°C–0.08%±0.02%0.08%
Differential nonlinearity, DNLMonotonic±1LSB
Relative accuracy, INL(3)TA = –40°C to +125°C±0.08%FSR
TA = –40°C to +85°C±0.024%
Offset errorTA = –40°C to +125°C–0.17%0.17%FSR
TA = –40°C to +85°C–0.1%0.1%
TA = 25°C–0.07%±0.01%0.07%
Offset error temperature coefficient±5ppm FSR/°C
Full-scale errorTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.16%0.16%
TA = 25°C–0.08%±0.015%0.08%
Full-scale error temperature coefficientInternal RSET±5ppm FSR/°C
External RSET±10
Gain errorInternal RSETTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.15%0.15%
TA = 25°C–0.08%±0.01%0.08%
External RSETTA = –40°C to +125°C–0.17%0.17%
TA = –40°C to +85°C–0.12%0.12%
TA = 25°C–0.05%±0.01%0.05%
Gain error temperature coefficientInternal RSET±3ppm FSR/°C
External RSET±8
Output current drift vs timeTA = 125°C, 1000 hrsInternal RSET±50ppm FSR
External RSET±25
CURRENT OUTPUT ACCURACY (4 mA TO 20 mA)(1)
Total unadjusted error, TUEInternal RSETTA = –40°C to +125°C–0.25%0.25%FSR
TA = 25°C–0.08%±0.02%0.08%
External RSETTA = –40°C to +125°C–0.29%0.29%
TA = –40°C to +85°C–0.25%0.25%
TA = 25°C–0.1%±0.02%0.1%
Differential nonlinearity, DNLMonotonic±1LSB
Relative accuracy, INL(3)TA = –40°C to +125°C±0.08%FSR
TA = –40°C to +85°C±0.024%
Offset errorInternal RSETTA = –40°C to +125°C–0.22%0.22%FSR
TA = –40°C to +85°C–0.2%0.2%
External RSETTA = –40°C to +125°C–0.2%0.2%
TA = –40°C to +85°C–0.18%0.18%
Internal and external RSET, TA = 25°C–0.07%±0.01%0.07%
Offset error temperature coefficient±3ppm FSR/°C
Full-scale errorInternal RSETTA = –40°C to +125°C–0.25%0.25%FSR
TA = 25°C–0 .08%±0.015%0.08%
External RSETTA = –40°C to +125°C–0.29%0.29%
TA = –40°C to +85°C–0.25%0.25%
TA = 25°C–0 .1%±0.015%0.1%
Full-scale error temperature coefficientInternal RSET±5ppm FSR/°C
External RSET±10
Gain errorInternal RSETTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.15%0.15%
TA = 25°C–0.08%±0.01%0.08%
External RSETTA = –40°C to +125°C–0.16%0.16%
TA = –40°C to +85°C–0.12%0.12%
TA = 25°C–0.05%±0.01%0.05%
Gain error temperature coefficientInternal RSET±3ppm FSR/°C
External RSET±8
Output current drift vs timeTA = 125°C, 1000 hrsInternal RSET±50ppm FSR
External RSET±75
CURRENT OUTPUT STAGE(2)
Loop compliance voltage(4)Output = 24 mAAVDD – 2V
Inductive load(5)50mH
DC PSRR1μA/V
Output impedanceCode = 0x800050MΩ
R3 RESISTOR
R3 resistor value364044Ω
R3 resistor temperature coefficient40ppm/°C
EXTERNAL REFERENCE INPUT
Reference input voltage4.9555.05V
External reference currentREFIN = 5.0 V30μA
Reference input capacitance10pF
INTERNAL REFERENCE OUTPUT
Reference outputTA = 25°C4.9955.005V
Reference temperature coefficient(2)TA = –40°C to +85°C±10ppm/°C
Output noise (0.1 Hz to 10 Hz)TA = 25°C14μVPP
Noise spectral densityTA = 25°C, 10 kHz185nV/√ Hz
Capacitive load600nF
Load current±5mA
Short-circuit currentREFOUT shorted to GND25mA
Load regulationAVDD = 24 V, TA = 25°C, sourcing55μV/mA
AVDD = 24 V, TA = 25°C, sinking120
Line regulation±1.2μV/V
DVDD INTERNAL REGULATOR
Output voltageAVDD = 24 V4.6V
Output load current(2)10mA
Load regulation3.5mV/mA
Line regulation1mV/V
Short-circuit currentAVDD = 24 V, to GND35mA
Capacitive load stability(2)2.5μF
DIGITAL INPUTS
High-level input voltage, VIH2V
Low-level input voltage, VIL3.6 V < AVDD < 5.5 V0.8V
2.7 V < AVDD < 3.6 V0.6
Hysteresis voltage0.4V
Input currentDVDD-EN, VIN ≤ 5 V–2.7μA
All pins other than DVDD-EN±1
Pin capacitancePer pin10pF
DIGITAL OUTPUTS
SDOLow-level output voltage, VOL, sinking 200 μA0.4V
HIigh-level output voltage, VOH, sourcing 200 μADVDD – 0.5
High-impedance leakage±1μA
ALARMLow-level output voltage, VOL10-kΩ pullup resistor to DVDD0.4V
2.5 mA0.6
High-impedance leakage±1μA
High-impedance output capacitance10pF
POWER SUPPLY
AVDD1036V
DVDDInternal regulator disabled2.75.5V
AIDDOutputs disabled, external DVDD3mA
Outputs disabled, internal DVDD4
Code = 0x0000, IOUT enabled3
DIDDVIH = DVDD, VIL = GND, interface idle1mA
Power dissipationAVDD = 36 V, IOUT = 0 mA, DVDD = 5 V95115mW
TEMPERATURE
Thermal alarm142°C
Thermal alarm hysteresis18°C
(1) DAC8750 and DAC7750 current output range is set by writing to RANGE bits in control register at address 0x55.
(2) Specified by design and characterization; not production tested.
(3) For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8750 and from code 0x0010 for DAC7750.
(4) Loop compliance voltage is defined as the voltage at the IOUT pin.
(5) For stability, use slew rate limit feature or add a capacitor between IOUT and GND