SLAS411D November 2004 – February 2016 DAC8811
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This design features the DAC8811 followed by a four-quadrant circuit for multiplying DACs. The circuit conditions the current output of an MDAC into a symmetrical bipolar voltage. The design uses an operational amplifier in a transimpedance configuration to convert the MDAC current into a voltage followed by an additional amplifier in a summing configuration to apply an offset voltage.
Using a multiplying DAC requires a transimpedance stage with an amplifier with minimal input offset voltage. The tolerance of the external resistors will vary depending on the goals of the application, but for optimal performance with the DAC8811 the tolerance should be 0.1 % for all of the external resistors. The summing stage amplifier also needs low input-offset voltage and enough slew rate for the output range desired.
The first stage of the design converts the current output of the MDAC (IOUT) to a voltage (VOUT) using an amplifier in a transimpedance configuration. A typical MDAC features an on-chip feedback resistor sized appropriately to match the ratio of the resistor values used in the DAC R-2R ladder. This resistor is available using the input shown in Figure 26 called RFB on the MDAC. The MDAC reference and the output of the transimpedance stage are then connected to the inverting input of the amplifier in the summing stage to produce the output that is defined by Equation 5.