SLAS411D November   2004  – February 2016 DAC8811

PRODUCTION DATA.  

  1. 1  Features
  2. 2  Applications
  3. 3  Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6  Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics: VDD = 5 V
    8. 7.8 Typical Characteristics: VDD = 2.7 V
  8. 8  Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Stability Circuit
      2. 8.3.2 Positive Voltage Output Circuit
      3. 8.3.3 Bipolar Output Circuit
      4. 8.3.4 Programmable Current Source Circuit
    4. 8.4 Device Functional Mode
    5. 8.5 Programming
      1. 8.5.1 DAC8811 Input Shift Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DRB Package
8-Pins VSON
Top View
DAC8811 po_DRB_slas411.gif
DGK Package
8-Pins VSSOP
Top View
DAC8811 po_DGK_slas411.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
CLK 1 I Clock input; positive edge triggered clocks data into shift register
SDI 2 I Serial register input; data loads directly into the shift register MSB first. Extra leading bits are ignored.
RFB 3 O Internal matching feedback resistor. Connect to external op amp output.
VREF 4 I DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code.
IOUT 5 O DAC current output. Connects to inverting terminal of external precision I/V op amp.
GND 6 G Analog and digital ground.
VDD 7 I Positive power supply input. Specified operating range of 2.7 V to 5.5 V.
CS 8 I Chip-select; active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for operation.