SBAS422B July 2007 – January 2018 DAC8881
PRODUCTION DATA.
When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode. When USB/BTC is connected to DGND, the device is in twos complement mode. In this case, the LDAC pin cannot be kept at logic level '0' or toggled when a hardware reset is issued before writing a valid DAC data.