SBAS422B July 2007 – January 2018 DAC8881
PRODUCTION DATA.
PARAMETER | CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fSCLK | Maximum clock frequency | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 40 | MHz | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 50 | MHz | |||
t1 | Minumum CS high time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 50 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 30 | ns | |||
t2 | CS falling edge to SCLK rising edge | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 8 | ns | |||
t3 | SCLK falling edge to CS falling edge setup time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |||
t4 | SCLK low time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |||
t5 | SCLK high time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 15 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |||
t6 | SCLK cycle time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 25 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 20 | ns | |||
t7 | SCLK rising edge to CS rising edge | 2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |||
t8 | Input data setup time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 8 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 5 | ns | |||
t9 | Input data hold time | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 5 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 5 | ns | |||
t14 | CS rising edge to LDAC falling edge | 2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 5 | ns | |||
t15 | LDAC pulse width | 2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD | 15 | ns | |
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD | 10 | ns |