SLASEL0B October 2019 – June 2020 DAC11001A , DAC81001 , DAC91001
PRODUCTION DATA.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Read/Write | Address | 00h | |||||||||||||
R/W | W | W | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
00h | DIS_TNH | UP_RATE | 0h | ||||||||||||
W | R/W | R/W | W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | Read/Write | R/W | N/A | Read when set to 1 or write when set to 0 |
30:24 | Address | W | N/A | 06h |
23:8 | 0000h | W | N/A | N/A |
7 | DIS_TNH | R/W | 0h | Disable track and hold:
0 : Track and hold enabled (default) 1 : Track and hold disabled |
6-4 | UP_RATE | R/W | 4h | DAC output max update rate:
000: 1 MHz with 38-MHz SCLK 001: 0.9 MHz with 34-MHz SCLK 010: 0.8 MHz with 31-MHz SCLK 011: 1.2 MHz with 45-MHz SCLK 100: 0.5 MHz with 21-MHz SCLK, (default) 101: 0.45 MHz with 18-MHz SCLK 110: 0.4 MHz with 16-MHz SCLK 111: 0.6 MHz with 24-MHz SCLK |
3:0 | 0h | W | N/A | N/A |