SBVS013E October   2001  – July 2022 DCR010503 , DCR010505 , DCR011203 , DCR011205 , DCR012403 , DCR012405

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolation
        1. 8.3.1.1 Operation or Functional Isolation
        2. 8.3.1.2 Basic or Enhanced Isolation
        3. 8.3.1.3 Working Voltage
        4. 8.3.1.4 Isolation Voltage Rating
        5. 8.3.1.5 Repeated High-Voltage Isolation Testing
      2. 8.3.2  Power Stage
      3. 8.3.3  Rectification
      4. 8.3.4  Regulator
      5. 8.3.5  Oscillator and Watchdog
      6. 8.3.6  ERROR Flag
      7. 8.3.7  Synchronization
      8. 8.3.8  Construction
      9. 8.3.9  Thermal Considerations
      10. 8.3.10 Decoupling – Ripple Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Disable and Enable
      2. 8.4.2 Regulated Output Disable and Enable
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DCR01 Single Voltage Output
      2. 9.1.2 Generating Two Positive Output Voltages
      3. 9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitor
        2. 9.2.2.2 Output Capacitor
        3. 9.2.2.3 Filter Capacitor
        4. 9.2.2.4 ERROR Flag
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

Carefully consider the layout of the PCB for the best results to be obtained.

Input and output power and ground planes provide a low-impedance path for the input and output power. For the output, the positive and negative voltage outputs conduct through wide traces to minimize losses.

A good-quality, low-ESR, ceramic capacitor placed as close as practical across the input reduces reflected ripple and ensure a smooth start-up.

A good-quality, low-ESR, ceramic capacitor placed as close as practical across the rectifier output terminal and output ground to provide the best ripple and noise performance.

The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.

If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance. Never connect a capacitor to the SYNC pin. If the SYNC pin is not being used it is advisable to place a guard ring (connected to input ground) around this pin to avoid any noise pick-up. Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects the performance of the oscillator.

Figure 11-1 shows a schematic for a single DCR01, SOP package device. Figure 11-2 and Figure 11-3 show a typical layout for the SOP package DCR01 device. The layout shows proper placement of capacitors and power planes.