SBASB20 September   2024 DDS39RF10 , DDS39RFS10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.4 Eye Scan Procedure

The PHY layer contains features for generating eye diagrams. A variety of different modes are supported (see ES register for list of modes). The following sections describe how to generate eye-scan data from the part and some approaches for building an eye-diagram.

  1. Configure the part for JESD204C operation by following the steps in the Startup Procedure for DUC Mode. Return here after setting JESD_EN=1. Eye-scan can be run with JESD204C bitstreams, but can also work with general PRBS input stimulus. Eye-scan is run on all enabled physical lanes simultaneously.
  2. Program ES to the desired eye-scan mode.
  3. If ES is less than 8, you must program ESVO to the desired voltage offset. For other modes, the eye-scan logic automatically adjusts the voltage offset of the eye-scan sampler.
  4. Program ESPO to the desired phase offset.
  5. Program ES_BIT_SELECT to a value from 0 to 19. Eye-scan analyzes every 20th received bit (decimate-by-20). ES_BIT_SELECT adjusts this decimation phase. For random stimulus, this does not impact the results. If the input has repeating patterns, this can affect the results.
  6. Program ESLEN to the desired number of samples. Higher settings give more consistent results.
  7. Set ECOUNT_CLR = 1 then set ECOUNT_CLR to clear the error counter. This step is recommended, but can be skipped if desired (e.g. to add up counts from multiple eye scan runs). This can also be skipped if ECOUNT won’t be used (for modes with ES of 8 or greater)
  8. Program ESRUN = 1 to start the scan.
  9. Poll ESDONE until ESDONE returns 1 for each of the lanes you want to run eye-scan on.
  10. If the selected eye-scan mode modified the eye-scan voltage offset (inner/outer/average modes), read ESVO_S to get the inner/outer/average eye boundary. For other eye-scan modes, read ECOUNT to return the number of mismatches (or matches) recorded.
  11. Program ESRUN = 0.
  12. Return to step 2 to run another eye-scan data collection process. The receiver can remain enabled during multiple iterations of steps 2-12.

There are two basic approaches to build an eye diagram using the eye-scan feature.

  1. 1. Fast approach using ESVO_S:
    1. Repeat the procedure above for each valid value of ESPO. For each value of ESPO, run an inner-eye analysis of zeros and ones. This locates the maximum zero (ESVOmax0 ) and minimum one (ESVOmin1) for each value of ESPO.
    2. All the cells of the eye between ESVOmax0 and ESVOmin1 (inclusive) can be colored black, and all other cells colored white.
    3. Additional detail can be added to the eye-diagram by including outer and/or average analysis (see ES). For example, the ESVO_S values produced from average analysis can be colored red, while all other values between and including the inner and outer values colored white.
  2. Detailed approach using ECOUNT:
    1. select an eye-scan mode that counts mismatches. Repeat the procedure outlined above for each valid value of ESVO and ESPO.
    2. After each run, record the value of ECOUNT (resetting ECOUNT before each run).
    3. Each eye-scan run corresponds to one cell of the eye-diagram. ESPO is the x-coordinate of the cell. ESVO is the y-coordinate of the cell. The intensity of the cell is proportional to ECOUNT/Nsamples, where Nsamples is the number of analyzed samples per run (determined by ESLEN).
    4. This approach takes much more time to run, but can provide a more granular eye-diagram.