SBASB20 September   2024 DDS39RF10 , DDS39RFS10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.3 Understanding Dual Edge Sampling Modes

Dual edge sampling modes (DES2XL/H) outputs unique samples on both the rising and falling edge of CLK, doubling the sample rate for the same clock frequency compared to NRZ, RTZ or RF modes. DES2XL/H modes generate the falling edge samples by digital interpolation. The 2x DES interpolator has an 80% passband bandwidth, 55dB stopband attenuation and can be configured as low pass or high pass (The response is shown in Figure 8-1). The DES interpolator is lowpass in DES2XL mode, passing the signal below 0.4*FCLK and removing the image above 0.6*FCLK. IN DES2XH mode signals above 0.6*FCLK are passed and the image below 0.4*FCLK is removed. In the transition band between 0.4*FCLK and 0.6*FCLK, the passband is attenuated by up to 6dB and the image attenuation is significantly reduce.

DDS39RF10 DDS39RFS10 DES Interpolator Frequency Response Figure 8-1 DES Interpolator Frequency Response

A non-50% CLK duty cycle results in an image of the signal at FCLK - FOUT. The amplitude of the image in DES2XL/H modes compared to NRZ/RF modes is shown in Figure 8-2. DES2XL provides 30+dB suppression over NRZ mode and DES2XH 20 to 30 B suppression over RF mode. This reduces the analog filtering required after the DAC to remove the unwanted images.

Figure 8-2 DES2XL/H Image compare to NRZ and RF Modes

The input clock frequency and input data rate is the same for NRZ, RF, RTZ, DES2XL and DES2XH modes - only the output waveform generated by the DAC is changed (See Section 7.3.1). Changing between modes only requires a different setting of the MXMODE register.

Figure 8-3 shows a comparison of DES2XL and NRZ mode for a fullscale tone at 3497MHz with 10GSPS clock frequency. In addition to the reduction of the image at FCLK - FOUT = 6743MHz, DES2XL mode can also suppress harmonics that in NRZ mode fold back below FCLK/2. In the plot, HD2 has an image at 3006MHz that is -65dBc in NRZ mode and -80dBc in DES2XL mode. Likewise, the HD3 image at 491MHz improves from -70dBc in NRZ mode to better than -90dBc in DES2XL mode. SFDR between 0 and FCLK/2 is limited by HD2 and therefore improves from 65 to 80dBc. Note that the non-linearity specifications for DES2XL mode in Section 6 are measured between 0 to FCLK/2 (as is NRZ mode), and for DES2XH mode between FCLK/2 and FCLK.

DDS39RF10 DDS39RFS10 Output Spectra Comparing DES2XL and NRZ Modes Figure 8-3 Output Spectra Comparing DES2XL and NRZ Modes

RF and DES2XH mode behave similarly. Figure 8-4 shows a tone at 7997MHz with 10GHz clock in RF and DES2XH modes. HD2 and HD3 have folded frequencies around 6GHz in NRZ mode, these are suppressed > 10dB in DES2XH mode.

DDS39RF10 DDS39RFS10 Output Spectra Comparing DES2XH and RF Modes Figure 8-4 Output Spectra Comparing DES2XH and RF Modes

One additional benefit of DES2XL compared to NRZ mode is an improvement in additive phase noise of approximately 6dB in the 1/f region of the offset frequency (see Figure 8-5). This is due to DES2XL using both the rising and falling edges of the clock, which cancels some common mode noise in the clock path. Since RF mode also uses the falling edge to generate the inverse sample, there is no significant difference between RF mode and DES2XH mode.

DDS39RF10 DDS39RFS10 Phase Noise vs Offset Frequency at 1GHz
fCLK = 10.24GHz
Figure 8-5 Phase Noise vs Offset Frequency at 1GHz

There are 3 small disadvantages of DES2XL and DES2XH modes to be aware of:

  1. the attenuation of the signal in the transition band of the DES interpolation filter between 0.4*FCLK and 0.6*FCLK
  2. An increased latency of 97 clock cycles. or 9.7ns with a 10GHz clock, due to the DES interpolation filter
  3. An increase in power of 250mW with a 10GHz clock, due to the DES interpolation filter