SBASB21 September   2024 DDS39RF12 , DDS39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1 Startup Procedure for DUC/Bypass Mode

The list below is the startup procedure for the device:

  1. Power up the device with ball RESET asserted using the procedure in Section 8.3.1.
  2. Apply CLK and then de-assert RESET.
  3. Wait for fuse values to be loaded (register FUSE_DONE returns 1).
  4. Set up all the operational parameters (registers can be programmed in any order):
    1. Program interpolation factor in the DUC_L register.
    2. Determine the total interpolation factor (LT), which is needed in the next steps. LT = DUC_L.
    3. Determine many sample streams are needed and program the JESD_M register.
    4. Select a JESD204C mode from Table 7-22. Make sure the selected mode supports the value of LT computed previously and the desired link layer encoding. Also make sure the mode supports the number of desired streams set in the JESD_M register. Program the mode number into the JMODE register.
    5. Program the JENC register to select 8b/10b or 64b/66b operation.
    6. Compute the value of R using Table 7-22 and the LT value computed earlier.
    7. Using Table 7-17 (8b/10b) or Table 7-18 (64b/66b), identify a row that matches the R value and DAC clock frequency. Program REFDIV, MPY, RATE and VRANGE according to the tables.
    8. If necessary, program LANE_SELn to bind the physical lanes 6 and 14 to logical lanes 0 and 1. Program LANE_INV if necessary to account for any lane inversion (differential pairs swapped on PCB).
    9. Program other common settings according to your desired usage (SUBCLASS, SFORMAT, SCR in JCTRL).
    10. If using 8b/10b encoding, program the KM1 register to set the K parameter. KM1 must match the link partner. Be sure to honor the constraint imposed by the KR parameter from Table 7-22.
    11. If subclass 1 operation is desired (SUBCLASS=1), you must also program RBD. Determine the appropriate value for RBD by referring to: Programming RBD.
    12. Optional Serdes parameters can also be programmed if necessary (that is, JPHY_CNTL, EQ_CNTL, EQZERO, LANE_EQn).
    13. Program any DAC or DUC related registers, for example the DAC_SRC register to route data to your desired DACs and configure MXMODE to set the DAC output mode.
  5. Program the transmitter (link partner, that is, FPGA or ASIC), and instruct the transmitter to begin transmission.
  6. Program JESD_EN=1 to start up the receiver.
  7. Program DP_EN=1 to enable the datapath. This is required to allow data to flow to the DAC. If only JESD204C diagnostics are performed, you can leave DP_EN at 0.
  8. Wait for the VDDDIG supply voltage to re-stablize as the supply current transient can result in a dip in the supply voltage. 80 microseconds is be sufficient, but this can be optimized based on actual measurements.
  9. If SUBCLASS=1, SYSREF is necessary to establish the LMFC/LEMC phase in the receiver. Follow this procedure:
    1. Using two separate transactions, program SYSREF_RECV_SLEEP=0 and then SYSREF_PROC_EN=1 (both in register SYSREF_CNTL).
    2. Program SYSREF_SEL to a known good value (see SYSREF Windowing for details on how to calculate SYSREF_SEL using the SYSREF windowing function).
    3. Program SYSREF_ALIGN_EN=1.
    4. Apply at least five SYSREF pulses to the SYSREF input. The period of each SYSREF cycle must meet the requirements in Table 7-3.
  10. Read the JESD_STATUS register to confirm operation of the link (LINK_UP field in JESD_STATUS = 1). If the LINK_UP field returns 0, verify these items:
    1. If the PLL_LOCKED field in JESD_STATUS returns 0, verify the correct PLL settings (REFDIV, MPY, RATE and VRANGE). Verify the CLK frequency is correct.
    2. If SUBCLASS = 1, and the ALIGNED field in JESD_STATUS returns 0, verify SYSREF has been applied and the SYSREF processor is enabled SYSREF_PROC_EN.
    3. If above are not the problem, then read the LANE_STATUSn (only read registers for logical lanes 0 to L-1). Identify if some lanes cannot acquire code group or block synchronization. If so, verify the transmitter has been programmed correctly. Verify LANE_SELn is programmed correctly. Consider performing PHY tests to verify/optimize PHY operation (PRBS testing using JTEST, eye-scan testing, or equalizer optimization).
  11. If coherency between multiple NCOs is required, the NCOs must be re-synchronized using one of the methods described in section NCO Synchronization for multi-device/deterministic synchronization, or using SPI_SYNC with NCO_SYNC_SRC if only internal NCO phase is required.
  12. To configure the part for a different mode, set DP_EN=0 and JESD_EN=0. Then return to step 4.