Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET.
Power off.
Refer to
Table 9-1 and
Figure 9-2 for critical power-up sequence delay requirements.
When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in
Section 6.4.
Drawing is not to scale and details are omitted for clarity.