DLPS123C february 2019 – july 2023 DLP2010
PRODUCTION DATA
PIN | TYPE | SIGNAL | DATA RATE | DESCRIPTION | PACKAGE NET LENGTH(2) (mm) | |
---|---|---|---|---|---|---|
NAME | NO. | |||||
DATA INPUTS | ||||||
D_N(0) | G4 | I | SubLVDS | Double | Data, Negative | 7.03 |
D_P(0) | G3 | I | SubLVDS | Double | Data, Positive | 7.03 |
D_N(1) | G8 | I | SubLVDS | Double | Data, Negative | 7.03 |
D_P(1) | G7 | I | SubLVDS | Double | Data, Positive | 7.03 |
D_N(2) | H5 | I | SubLVDS | Double | Data, Negative | 7.02 |
D_P(2) | H6 | I | SubLVDS | Double | Data, Positive | 7.02 |
D_N(3) | H1 | I | SubLVDS | Double | Data, Negative | 7.00 |
D_P(3) | H2 | I | SubLVDS | Double | Data, Positive | 7.00 |
DCLK_N | H9 | I | SubLVDS | Double | Clock, Negative | 7.03 |
DCLK_P | H10 | I | SubLVDS | Double | Clock, Positive | 7.03 |
CONTROL INPUTS | ||||||
DMD_DEN_ARSTZ | G12 | I | LPSDR(1) | Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. | 5.72 | |
LS_CLK | G19 | I | LPSDR | Single | Clock for low-speed interface | 3.54 |
LS_WDATA | G18 | I | LPSDR | Single | Write data for low-speed interface | 3.54 |
LS_RDATA | G11 | O | LPSDR | Single | Read data for low-speed interface | 8.11 |
POWER | ||||||
VBIAS(3) | H17 | Power | Supply voltage for positive bias level at micromirrors | |||
VOFFSET(3) | H13 | Power | Supply voltage for HVCMOS core logic. Includes: supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors |
|||
VRESET(3) | H18 | Power | Supply voltage for negative reset level at micromirrors | |||
VDD(3) | G20 | Power | Supply voltage for micromirror low voltage CMOS core logic includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes. | |||
VDD | H14 | Power | ||||
VDD | H15 | Power | ||||
VDD | H16 | Power | ||||
VDD | H19 | Power | ||||
VDD | H20 | Power | ||||
VDDI(3) | G1 | Power | Supply voltage for SubLVDS receivers | |||
VDDI | G2 | Power | ||||
VDDI | G5 | Power | ||||
VDDI | G6 | Power | ||||
VSS(3) | G9 | Ground | Ground. Common return for all power. | |||
VSS | G10 | Ground | ||||
VSS | G13 | Ground | ||||
VSS | G14 | Ground | ||||
VSS | G15 | Ground | ||||
VSS | G16 | Ground | ||||
VSS | G17 | Ground | ||||
VSS | H3 | Ground | ||||
VSS | H4 | Ground | ||||
VSS | H7 | Ground | ||||
VSS | H8 | Ground | ||||
VSS | H11 | Ground | ||||
VSS | H12 | Ground |
NUMBER | SYSTEM BOARD | NUMBER | SYSTEM BOARD |
---|---|---|---|
A2 | Do not connect | D2 | Do not connect |
A3 | Do not connect | D3 | Do not connect |
A4 | Do not connect | D17 | Do not connect |
A5 | Do not connect | D18 | Do not connect |
A6 | Do not connect | ||
A7 | Do not connect | E2 | Do not connect |
A8 | Do not connect | E3 | Do not connect |
A9 | Do not connect | E17 | Do not connect |
A10 | Do not connect | E18 | Do not connect |
A11 | Do not connect | ||
A12 | Do not connect | F1 | Do not connect |
A13 | Do not connect | F2 | Do not connect |
A14 | Do not connect | F3 | Do not connect |
A15 | Do not connect | F4 | Do not connect |
A16 | Do not connect | F5 | Do not connect |
A17 | Do not connect | F6 | Do not connect |
A18 | Do not connect | F7 | Do not connect |
A19 | Do not connect | F8 | Do not connect |
F9 | Do not connect | ||
B2 | Do not connect | F10 | Do not connect |
B3 | Do not connect | F11 | Do not connect |
B17 | Do not connect | F12 | Do not connect |
B18 | Do not connect | F13 | Do not connect |
F14 | Do not connect | ||
C2 | Do not connect | F15 | Do not connect |
C3 | Do not connect | F16 | Do not connect |
C17 | Do not connect | F17 | Do not connect |
C18 | Do not connect | F18 | Do not connect |
F19 | Do not connect |